source: branches/backfire/target/linux/generic-2.6/patches-2.6.30/990-fix_feroceon_vfp_handling.patch @ 29023

Last change on this file since 29023 was 29023, checked in by florian, 5 years ago

refresh 2.6.30 patches

File size: 2.5 KB
  • arch/arm/vfp/vfphw.S

    From: Catalin Marinas <catalin.marinas@arm.com>
    Date: Sat, 30 May 2009 13:00:18 +0000 (+0100)
    Subject: Fix the VFP handling on the Feroceon CPU
    X-Git-Url: http://www.linux-arm.org/git?p=linux-2.6.git;a=commitdiff_plain;h=85d6943af50537d3aec58b967ffbd3fec88453e9;hp=26584853a44c58f3d6ac7360d697a2ddcd1a3efa
    
    Fix the VFP handling on the Feroceon CPU
    
    This CPU generates synchronous VFP exceptions in a non-standard way -
    the FPEXC.EX bit set but without the FPSCR.IXE bit being set like in the
    VFP subarchitecture 1 or just the FPEXC.DEX bit like in VFP
    subarchitecture 2. The main problem is that the faulty instruction
    (which needs to be emulated in software) will be restarted several times
    (normally until a context switch disables the VFP). This patch ensures
    that the VFP exception is treated as synchronous.
    
    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Nicolas Pitre <nico@cam.org>
    ---
    
    a b ENTRY(vfp_support_entry) 
    100100        beq     no_old_VFP_process 
    101101        VFPFSTMIA r4, r5                @ save the working registers 
    102102        VFPFMRX r5, FPSCR               @ current status 
     103#ifndef CONFIG_CPU_FEROCEON 
    103104        tst     r1, #FPEXC_EX           @ is there additional state to save? 
    104105        beq     1f 
    105106        VFPFMRX r6, FPINST              @ FPINST (only if FPEXC.EX is set) 
    ENTRY(vfp_support_entry) 
    107108        beq     1f 
    108109        VFPFMRX r8, FPINST2             @ FPINST2 if needed (and present) 
    1091101: 
     111#endif 
    110112        stmia   r4, {r1, r5, r6, r8}    @ save FPEXC, FPSCR, FPINST, FPINST2 
    111113                                        @ and point r4 at the word at the 
    112114                                        @ start of the register dump 
    no_old_VFP_process: 
    119121        VFPFLDMIA r10, r5               @ reload the working registers while 
    120122                                        @ FPEXC is in a safe state 
    121123        ldmia   r10, {r1, r5, r6, r8}   @ load FPEXC, FPSCR, FPINST, FPINST2 
     124#ifndef CONFIG_CPU_FEROCEON 
    122125        tst     r1, #FPEXC_EX           @ is there additional state to restore? 
    123126        beq     1f 
    124127        VFPFMXR FPINST, r6              @ restore FPINST (only if FPEXC.EX is set) 
    no_old_VFP_process: 
    126129        beq     1f 
    127130        VFPFMXR FPINST2, r8             @ FPINST2 if needed (and present) 
    1281311: 
     132#endif 
    129133        VFPFMXR FPSCR, r5               @ restore status 
    130134 
    131135check_for_exception: 
  • arch/arm/vfp/vfpmodule.c

    a b void VFP_bounce(u32 trigger, u32 fpexc, 
    253253        } 
    254254 
    255255        if (fpexc & FPEXC_EX) { 
     256#ifndef CONFIG_CPU_FEROCEON 
    256257                /* 
    257258                 * Asynchronous exception. The instruction is read from FPINST 
    258259                 * and the interrupted instruction has to be restarted. 
    259260                 */ 
    260261                trigger = fmrx(FPINST); 
    261262                regs->ARM_pc -= 4; 
     263#endif 
    262264        } else if (!(fpexc & FPEXC_DEX)) { 
    263265                /* 
    264266                 * Illegal combination of bits. It can be caused by an 
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