source: trunk/package/uboot-ifxmips/files/board/danube/danube.c @ 11601

Last change on this file since 11601 was 11601, checked in by nbd, 8 years ago

move ifxmips uboot to package/

File size: 4.7 KB
Line 
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <asm/addrspace.h>
27#include <asm/danube.h>
28
29#ifdef DANUBE_USE_DDR_RAM
30long int initdram(int board_type)
31{
32        return (1024*1024*DANUBE_DDR_RAM_SIZE);
33}
34#else
35extern uint danube_get_cpuclk(void);
36
37static ulong max_sdram_size(void)     /* per Chip Select */
38{
39        /* The only supported SDRAM data width is 16bit.
40         */
41#define CFG_DW  4
42
43        /* The only supported number of SDRAM banks is 4.
44         */
45#define CFG_NB  4
46
47        ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
48        int   cols   = cfgpb0 & 0xF;
49        int   rows   = (cfgpb0 & 0xF0) >> 4;
50        ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
51
52        return size;
53}
54
55/*
56 * Check memory range for valid RAM. A simple memory test determines
57 * the actually available RAM size between addresses `base' and
58 * `base + maxsize'.
59 */
60
61static long int dram_size(long int *base, long int maxsize)
62{
63        volatile long int *addr;
64        ulong cnt, val;
65        ulong save[32];                 /* to make test non-destructive */
66        unsigned char i = 0;
67
68        for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
69                addr = base + cnt;              /* pointer arith! */
70
71                save[i++] = *addr;
72                *addr = ~cnt;
73        }
74
75        /* write 0 to base address */
76        addr = base;
77        save[i] = *addr;
78        *addr = 0;
79
80        /* check at base address */
81        if ((val = *addr) != 0) {
82                *addr = save[i];
83                return (0);
84        }
85
86        for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
87                addr = base + cnt;              /* pointer arith! */
88
89                val = *addr;
90                *addr = save[--i];
91
92                if (val != (~cnt)) {
93                        return (cnt * sizeof (long));
94                }
95        }
96        return (maxsize);
97}
98
99long int initdram(int board_type)
100{
101        int   rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
102        ulong size, max_size       = 0;
103        ulong our_address;
104
105        /* load t9 into our_address */ 
106        asm volatile ("move %0, $25" : "=r" (our_address) :);
107
108        /* Can't probe for RAM size unless we are running from Flash.
109         * find out whether running from DRAM or Flash.
110         */
111        if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
112        {
113                return max_sdram_size();
114        }
115
116        for (cols = 0x8; cols <= 0xC; cols++)
117        {
118                for (rows = 0xB; rows <= 0xD; rows++)
119                {
120                        *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
121                                                   (rows << 4) | cols;
122                        size = dram_size((ulong *)CFG_SDRAM_BASE,
123                                                             max_sdram_size());
124
125                        if (size > max_size)
126                        {
127                                best_val = *DANUBE_SDRAM_MC_CFGPB0;
128                                max_size = size;
129                        }
130                }
131        }
132
133        *DANUBE_SDRAM_MC_CFGPB0 = best_val;
134        return max_size;
135}
136#endif
137
138int checkboard (void)
139{
140        /*    No such register in Amazon */
141#if 0
142        unsigned long chipid = *AMAZON_MCD_CHIPID;
143        int part_num;
144
145        puts ("Board: AMAZON ");
146        part_num = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
147        switch (part_num) {
148        case AMAZON_CHIPID_STANDARD:
149                printf ("Standard Version, ");
150                break;
151        case AMAZON_CHIPID_YANGTSE:
152                printf ("Yangtse Version, ");
153                break;
154        default:
155                printf ("Unknown Part Number 0x%x ", part_num);
156                break;
157        }
158
159        printf ("Chip V1.%ld, ", AMAZON_MCD_CHIPID_VERSION_GET(chipid));
160     
161
162        printf("CPU Speed %d MHz\n", danube_get_cpuclk()/1000000);
163       
164#endif
165        return 0;
166}
167
168
169/*
170 * Disk On Chip (NAND) Millenium initialization.
171 * The NAND lives in the CS2* space
172 */
173#if (CONFIG_COMMANDS & CFG_CMD_NAND)
174extern void
175nand_probe(ulong physadr);
176
177#define AT91_SMARTMEDIA_BASE 0x40000000  /* physical address to access memory on NCS3 */
178void
179nand_init(void)
180{
181        int devtype;
182        /* Configure EBU */
183//TODO: should we keep this?
184        //Set GPIO23 to be Flash CS1;
185        *DANUBE_GPIO_P1_ALTSEL0 = *DANUBE_GPIO_P1_ALTSEL0 | (1<<7);
186        *DANUBE_GPIO_P1_ALTSEL1 = *DANUBE_GPIO_P1_ALTSEL1 & ~(1<<7);
187        *DANUBE_GPIO_P1_DIR = *DANUBE_GPIO_P1_DIR | (1<<7) ;
188        *DANUBE_GPIO_P1_OD = *DANUBE_GPIO_P1_OD | (1<<7) ;
189       
190        *EBU_ADDR_SEL_1 = (NAND_BASE_ADDRESS&0x1fffff00)|0x31;
191        /* byte swap;minimum delay*/
192        *EBU_CON_1      = 0x40C155;
193        *EBU_NAND_CON   = 0x000005F3;
194
195        /* Set bus signals to inactive */
196         NAND_READY_CLEAR;
197
198         NAND_CE_CLEAR;
199         nand_probe(NAND_BASE_ADDRESS);
200
201
202
203        //nand_probe(AT91_SMARTMEDIA_BASE);
204}
205#endif
206
207
208
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