source: trunk/package/uboot-ifxmips/files/include/configs/danube.h @ 18700

Last change on this file since 18700 was 18700, checked in by blogic, 6 years ago

make uboot work on arcaydian board

File size: 8.4 KB
Line 
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains the configuration parameters for the danube board.
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define  USE_REFERENCE_BOARD
32//#define   USE_EVALUATION_BOARD
33
34//#define   DANUBE_BOOT_FROM_EBU
35#define   DANUBE_USE_DDR_RAM
36
37#ifdef DANUBE_USE_DDR_RAM
38//#define  DANUBE_DDR_RAM_111M
39//#define DANUBE_DDR_RAM_166M
40//#define PROMOSDDR400
41//#define DDR_SAMSUNG_166M
42#define DDR_PSC_166M
43//#define DANUBE_DDR_RAM_133M
44#define DANUBE_DDR_RAM_SIZE     32      /* 32M DDR-DRAM for reference board */
45#endif
46
47#define CONFIG_LZMA             1       /* use LZMA for compression */
48
49#define CLK_OUT2_25MHZ
50#define CONFIG_MIPS32           1       /* MIPS 4Kc CPU core    */
51#define CONFIG_IFX_MIPS         1       /* in an Infineon chip  */
52#define CONFIG_DANUBE           1       /* on a danube Board    */
53#define RAM_SIZE                0x2000000 /*32M ram*/
54
55#define CPU_CLOCK_RATE          235000000   /* 235 MHz clock for the MIPS core */
56
57#define INFINEON_EBU_BOOTCFG    0x688C688C      /* CMULT = 8 for 150 MHz */
58
59#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
60
61#define CONFIG_BAUDRATE         115200
62
63#define DEBUG_PARSER            2
64
65/* valid baudrates */
66#define CFG_BAUDRATE_TABLE      { 300, 9600, 19200, 38400, 57600, 115200 }
67
68#ifndef CFG_BOOTSTRAP_CODE
69#define CONFIG_TIMESTAMP                /* Print image info with timestamp */
70#endif
71
72#define CONFIG_PREBOOT  "echo;" \
73        "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
74        "echo"
75
76#undef  CONFIG_BOOTARGS
77/* by MarsLin 2005/05/10, to support different hardware configuations */
78//#define CONFIG_EXTRA_ENV_SETTINGS     <configs/ifx_extra_env.h>
79#define CONFIG_EXTRA_ENV_SETTINGS \
80        "ethaddr=11:22:33:44:55:66\0" \
81        "serverip=192.168.45.100\0" \
82        "ipaddr=192.168.45.108\0"  \
83        "ram_addr=0x80500000\0" \
84        "kernel_addr=0xb0030000\0" \
85        "flashargs=setenv bootargs rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
86        "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} init=/etc/preinit\0" \
87        "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
88        "addmisc=setenv bootargs ${bootargs} console=ttyS1,115200 ethaddr=${ethaddr} ${mtdparts}\0" \
89        "flash_flash=run flashargs addip addmisc;bootm ${kernel_addr}\0" \
90        "flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \
91        "net_flash=run load_kernel flashargs addip addmisc;bootm ${ram_addr}\0" \
92        "net_nfs=run load_kernel nfsargs addip addmisc;bootm ${ram_addr}\0" \
93        "load_kernel=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-uImage\0" \
94        "update_uboot=tftp 0x80500000 u-boot.ifx;era 1:0-10; cp.b 0x80500000 0xb0000000 0x10000\0" \
95        "update_openwrt=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-squashfs.image; era ${kernel_addr} +${filesize} 0; cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
96
97#define CONFIG_BOOTCOMMAND      "run flash_flash"
98
99#define CONFIG_COMMANDS_YES     (CONFIG_CMD_DFL | \
100                                 CFG_CMD_ASKENV         | \
101                                 CFG_CMD_NET    )
102
103#define CONFIG_COMMANDS_NO      (CFG_CMD_NFS            | \
104                                 CFG_CMD_FPGA           | \
105                                 CFG_CMD_IMLS           | \
106                                 CFG_CMD_ITEST          | \
107                                 CFG_CMD_XING           | \
108                                 CFG_CMD_IMI            | \
109                                 CFG_CMD_BMP            | \
110                                 CFG_CMD_BOOTD          | \
111                                 CFG_CMD_CONSOLE        | \
112                                 CFG_CMD_LOADS          | \
113                                 CFG_CMD_LOADB          )
114
115#define CONFIG_COMMANDS         (CONFIG_COMMANDS_YES & ~CONFIG_COMMANDS_NO)
116
117#if 0
118                                 CFG_CMD_DHCP
119                                 CFG_CMD_ELF
120                                 CFG_CMD_NAND
121#endif
122
123#include <cmd_confdefs.h>
124
125/*
126 * Miscellaneous configurable options
127 */
128#define CFG_LONGHELP                            /* undef to save memory      */
129#define CFG_PROMPT              "DANUBE # "     /* Monitor Command Prompt    */
130#define CFG_CBSIZE              256             /* Console I/O Buffer Size   */
131#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
132#define CFG_MAXARGS             16              /* max number of command args*/
133
134#define CFG_MALLOC_LEN          128*1024
135
136#define CFG_BOOTPARAMS_LEN      128*1024
137
138#define CFG_HZ       (CPU_CLOCK_RATE / 2)
139
140#define CFG_LOAD_ADDR           0x80100000      /* default load address */
141
142#define CFG_MEMTEST_START       0x80100000
143#define CFG_MEMTEST_END         0x80400000
144
145/*-----------------------------------------------------------------------
146 * FLASH and environment organization
147 */
148#define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
149#define CFG_MAX_FLASH_SECT      (135)   /* max number of sectors on one chip */
150
151#define PHYS_FLASH_1            0xB0000000 /* Flash Bank #1 */
152#define PHYS_FLASH_2            0xB4000000 /* Flash Bank #2 */
153
154#define BOOTSTRAP_TEXT_BASE 0xb0000000 
155
156/* The following #defines are needed to get flash environment right */
157#define CFG_MONITOR_BASE        UBOOT_RAM_TEXT_BASE     /* board/danube/config.mk. = 0xA0800000 */
158#define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE     /* board/danube/config.mk. = 0xA0800000 */
159#define CFG_MONITOR_LEN         (256 << 10)
160
161#define CFG_INIT_SP_OFFSET      0x400000
162
163#define CFG_FLASH_BASE          PHYS_FLASH_1
164
165/* timeout values are in ticks */
166#define CFG_FLASH_ERASE_TOUT    (20 * CFG_HZ) /* Timeout for Flash Erase */
167#define CFG_FLASH_WRITE_TOUT    (20 * CFG_HZ) /* Timeout for Flash Write */
168
169#define CFG_ENV_IS_IN_FLASH     1
170//#define CFG_ENV_IS_NOWHERE    1
171//#define CFG_ENV_IS_IN_NVRAM   1
172/* Address and size of Primary Environment Sector       */
173#define CFG_ENV_ADDR            0xB0020000
174#define CFG_ENV_SIZE            0x10000
175
176#define CONFIG_FLASH_16BIT
177
178#define CONFIG_NR_DRAM_BANKS    1
179
180#define CONFIG_DANUBE_SWITCH
181#define CONFIG_NET_MULTI
182#define CONFIG_ENV_OVERWRITE
183
184#define EXCEPTION_BASE  0x200
185
186/**
187 *\brief definition for nand
188 *
189 */
190#define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
191#define NAND_ChipID_UNKNOWN     0x00
192#define SECTORSIZE 512
193#define NAND_MAX_FLOORS 1
194#define NAND_MAX_CHIPS 1
195
196
197#define ADDR_COLUMN 1
198#define ADDR_PAGE 2
199#define ADDR_COLUMN_PAGE 3
200
201
202#define AT91_SMART_MEDIA_ALE (1 << 22)  /* our ALE is AD22 */
203#define AT91_SMART_MEDIA_CLE (1 << 21)  /* our CLE is AD21 */
204
205#define NAND_DISABLE_CE(nand)
206#define NAND_ENABLE_CE(nand)
207#define NAND_WAIT_READY(nand)
208#define WRITE_NAND_COMMAND(d, adr)
209#define WRITE_NAND_ADDRESS(d, adr)
210#define WRITE_NAND(d, adr)
211#define READ_NAND(adr)
212/* the following are NOP's in our implementation */
213#define NAND_CTL_CLRALE(nandptr)
214#define NAND_CTL_SETALE(nandptr)
215#define NAND_CTL_CLRCLE(nandptr)
216#define NAND_CTL_SETCLE(nandptr)
217
218
219
220#define NAND_BASE_ADDRESS  0xB4000000
221
222#define NAND_WRITE(addr, val)     *((u8*)(NAND_BASE_ADDRESS | (addr))) = val;while((*EBU_NAND_WAIT & 0x08) == 0);
223#define NAND_READ(addr, val)      val = *((u8*)(NAND_BASE_ADDRESS | (addr)))
224#define NAND_CE_SET
225#define NAND_CE_CLEAR
226#define NAND_READY       ( ((*EBU_NAND_WAIT)&0x07) == 7)
227#define NAND_READY_CLEAR  *EBU_NAND_WAIT = 0;
228#define WRITE_CMD    0x18
229#define WRITE_ADDR   0x14
230#define WRITE_LADDR  0x10
231#define WRITE_DATA  0x10
232#define READ_DATA    0x10
233#define READ_LDATA   0x00
234#define ACCESS_WAIT
235#define IFX_ATC_NAND 0xc176
236#define IFX_BTC_NAND 0xc166
237#define ST_512WB2_NAND 0x2076
238
239#define NAND_OK              0x00000000    /* Bootstrap succesful, start address in BOOT_RVEC */
240#define NAND_ERR             0x80000000
241#define NAND_ACC_TIMEOUT     (NAND_ERR | 0x00000001)
242#define NAND_ACC_ERR         (NAND_ERR | 0x00000002)
243
244
245/*****************************************************************************
246 * DANUBE
247 *****************************************************************************/
248/* lock cache for C program stack */
249/* points to ROM */
250/* stack size is 16K */
251#define LOCK_DCACHE_ADDR        0x9FC00000
252#define LOCK_DCACHE_SIZE        0x1000
253
254/*
255 * Memory layout
256 */
257#define CFG_SDRAM_BASE          0x80000000
258#define CFG_SDRAM_BASE_UNCACHE  0xA0000000
259#define CFG_CACHE_LOCK_SIZE  LOCK_DCACHE_SIZE
260
261/*
262 * Cache settings
263 */
264#define CFG_CACHE_SIZE   16384
265#define CFG_CACHE_LINES  32
266#define CFG_CACHE_WAYS   4
267#define CFG_CACHE_SETS   128
268
269#define CFG_ICACHE_SIZE   CFG_CACHE_SIZE
270#define CFG_DCACHE_SIZE   CFG_CACHE_SIZE
271#define CFG_CACHELINE_SIZE  CFG_CACHE_LINES
272
273#endif  /* __CONFIG_H */
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