source: trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @ 27064

Last change on this file since 27064 was 27064, checked in by juhosg, 5 years ago

ar71xx: add WMAC initialization code for the AR933X SoCs

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File size: 23.1 KB
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1/*
2 *  Atheros AR71xx SoC specific definitions
3 *
4 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 *  Parts of this file are based on Atheros 2.6.15 BSP
9 *  Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 *  This program is free software; you can redistribute it and/or modify it
12 *  under the terms of the GNU General Public License version 2 as published
13 *  by the Free Software Foundation.
14 */
15
16#ifndef __ASM_MACH_AR71XX_H
17#define __ASM_MACH_AR71XX_H
18
19#include <linux/types.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/bitops.h>
23
24#ifndef __ASSEMBLER__
25
26#define AR71XX_PCI_MEM_BASE     0x10000000
27#define AR71XX_PCI_MEM_SIZE     0x08000000
28#define AR71XX_APB_BASE         0x18000000
29#define AR71XX_GE0_BASE         0x19000000
30#define AR71XX_GE0_SIZE         0x01000000
31#define AR71XX_GE1_BASE         0x1a000000
32#define AR71XX_GE1_SIZE         0x01000000
33#define AR71XX_EHCI_BASE        0x1b000000
34#define AR71XX_EHCI_SIZE        0x01000000
35#define AR71XX_OHCI_BASE        0x1c000000
36#define AR71XX_OHCI_SIZE        0x01000000
37#define AR7240_OHCI_BASE        0x1b000000
38#define AR7240_OHCI_SIZE        0x01000000
39#define AR71XX_SPI_BASE         0x1f000000
40#define AR71XX_SPI_SIZE         0x01000000
41
42#define AR71XX_DDR_CTRL_BASE    (AR71XX_APB_BASE + 0x00000000)
43#define AR71XX_DDR_CTRL_SIZE    0x10000
44#define AR71XX_CPU_BASE         (AR71XX_APB_BASE + 0x00010000)
45#define AR71XX_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
46#define AR71XX_UART_SIZE        0x10000
47#define AR71XX_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
48#define AR71XX_USB_CTRL_SIZE    0x10000
49#define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
50#define AR71XX_GPIO_SIZE        0x10000
51#define AR71XX_PLL_BASE         (AR71XX_APB_BASE + 0x00050000)
52#define AR71XX_PLL_SIZE         0x10000
53#define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
54#define AR71XX_RESET_SIZE       0x10000
55#define AR71XX_MII_BASE         (AR71XX_APB_BASE + 0x00070000)
56#define AR71XX_MII_SIZE         0x10000
57#define AR71XX_SLIC_BASE        (AR71XX_APB_BASE + 0x00090000)
58#define AR71XX_SLIC_SIZE        0x10000
59#define AR71XX_DMA_BASE         (AR71XX_APB_BASE + 0x000A0000)
60#define AR71XX_DMA_SIZE         0x10000
61#define AR71XX_STEREO_BASE      (AR71XX_APB_BASE + 0x000B0000)
62#define AR71XX_STEREO_SIZE      0x10000
63
64#define AR724X_PCI_CRP_BASE     (AR71XX_APB_BASE + 0x000C0000)
65#define AR724X_PCI_CRP_SIZE     0x100
66
67#define AR724X_PCI_CTRL_BASE    (AR71XX_APB_BASE + 0x000F0000)
68#define AR724X_PCI_CTRL_SIZE    0x100
69
70#define AR91XX_WMAC_BASE        (AR71XX_APB_BASE + 0x000C0000)
71#define AR91XX_WMAC_SIZE        0x30000
72
73#define AR933X_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
74#define AR933X_UART_SIZE        0x14
75#define AR933X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
76#define AR933X_WMAC_SIZE        0x20000
77
78#define AR934X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
79#define AR934X_WMAC_SIZE        0x20000
80
81#define AR71XX_MEM_SIZE_MIN     0x0200000
82#define AR71XX_MEM_SIZE_MAX     0x10000000
83
84#define AR71XX_CPU_IRQ_BASE     0
85#define AR71XX_MISC_IRQ_BASE    8
86#define AR71XX_MISC_IRQ_COUNT   32
87#define AR71XX_GPIO_IRQ_BASE    40
88#define AR71XX_GPIO_IRQ_COUNT   32
89#define AR71XX_PCI_IRQ_BASE     72
90#define AR71XX_PCI_IRQ_COUNT    8
91
92#define AR71XX_CPU_IRQ_IP2      (AR71XX_CPU_IRQ_BASE + 2)
93#define AR71XX_CPU_IRQ_USB      (AR71XX_CPU_IRQ_BASE + 3)
94#define AR71XX_CPU_IRQ_GE0      (AR71XX_CPU_IRQ_BASE + 4)
95#define AR71XX_CPU_IRQ_GE1      (AR71XX_CPU_IRQ_BASE + 5)
96#define AR71XX_CPU_IRQ_MISC     (AR71XX_CPU_IRQ_BASE + 6)
97#define AR71XX_CPU_IRQ_TIMER    (AR71XX_CPU_IRQ_BASE + 7)
98
99#define AR71XX_MISC_IRQ_TIMER   (AR71XX_MISC_IRQ_BASE + 0)
100#define AR71XX_MISC_IRQ_ERROR   (AR71XX_MISC_IRQ_BASE + 1)
101#define AR71XX_MISC_IRQ_GPIO    (AR71XX_MISC_IRQ_BASE + 2)
102#define AR71XX_MISC_IRQ_UART    (AR71XX_MISC_IRQ_BASE + 3)
103#define AR71XX_MISC_IRQ_WDOG    (AR71XX_MISC_IRQ_BASE + 4)
104#define AR71XX_MISC_IRQ_PERFC   (AR71XX_MISC_IRQ_BASE + 5)
105#define AR71XX_MISC_IRQ_OHCI    (AR71XX_MISC_IRQ_BASE + 6)
106#define AR71XX_MISC_IRQ_DMA     (AR71XX_MISC_IRQ_BASE + 7)
107#define AR71XX_MISC_IRQ_TIMER2  (AR71XX_MISC_IRQ_BASE + 8)
108#define AR71XX_MISC_IRQ_TIMER3  (AR71XX_MISC_IRQ_BASE + 9)
109#define AR71XX_MISC_IRQ_TIMER4  (AR71XX_MISC_IRQ_BASE + 10)
110#define AR71XX_MISC_IRQ_DDR_PERF        (AR71XX_MISC_IRQ_BASE + 11)
111#define AR71XX_MISC_IRQ_ENET_LINK       (AR71XX_MISC_IRQ_BASE + 12)
112
113#define AR71XX_GPIO_IRQ(_x)     (AR71XX_GPIO_IRQ_BASE + (_x))
114
115#define AR71XX_PCI_IRQ_DEV0     (AR71XX_PCI_IRQ_BASE + 0)
116#define AR71XX_PCI_IRQ_DEV1     (AR71XX_PCI_IRQ_BASE + 1)
117#define AR71XX_PCI_IRQ_DEV2     (AR71XX_PCI_IRQ_BASE + 2)
118#define AR71XX_PCI_IRQ_CORE     (AR71XX_PCI_IRQ_BASE + 4)
119
120extern u32 ar71xx_ahb_freq;
121extern u32 ar71xx_cpu_freq;
122extern u32 ar71xx_ddr_freq;
123extern u32 ar71xx_ref_freq;
124
125enum ar71xx_soc_type {
126        AR71XX_SOC_UNKNOWN,
127        AR71XX_SOC_AR7130,
128        AR71XX_SOC_AR7141,
129        AR71XX_SOC_AR7161,
130        AR71XX_SOC_AR7240,
131        AR71XX_SOC_AR7241,
132        AR71XX_SOC_AR7242,
133        AR71XX_SOC_AR9130,
134        AR71XX_SOC_AR9132,
135        AR71XX_SOC_AR9330,
136        AR71XX_SOC_AR9331,
137        AR71XX_SOC_AR9341,
138        AR71XX_SOC_AR9342,
139        AR71XX_SOC_AR9344,
140};
141
142extern enum ar71xx_soc_type ar71xx_soc;
143
144/*
145 * PLL block
146 */
147#define AR71XX_PLL_REG_CPU_CONFIG       0x00
148#define AR71XX_PLL_REG_SEC_CONFIG       0x04
149#define AR71XX_PLL_REG_ETH0_INT_CLOCK   0x10
150#define AR71XX_PLL_REG_ETH1_INT_CLOCK   0x14
151
152#define AR71XX_PLL_DIV_SHIFT            3
153#define AR71XX_PLL_DIV_MASK             0x1f
154#define AR71XX_CPU_DIV_SHIFT            16
155#define AR71XX_CPU_DIV_MASK             0x3
156#define AR71XX_DDR_DIV_SHIFT            18
157#define AR71XX_DDR_DIV_MASK             0x3
158#define AR71XX_AHB_DIV_SHIFT            20
159#define AR71XX_AHB_DIV_MASK             0x7
160
161#define AR71XX_ETH0_PLL_SHIFT           17
162#define AR71XX_ETH1_PLL_SHIFT           19
163
164#define AR724X_PLL_REG_CPU_CONFIG       0x00
165#define AR724X_PLL_REG_PCIE_CONFIG      0x18
166
167#define AR724X_PLL_DIV_SHIFT            0
168#define AR724X_PLL_DIV_MASK             0x3ff
169#define AR724X_PLL_REF_DIV_SHIFT        10
170#define AR724X_PLL_REF_DIV_MASK         0xf
171#define AR724X_AHB_DIV_SHIFT            19
172#define AR724X_AHB_DIV_MASK             0x1
173#define AR724X_DDR_DIV_SHIFT            22
174#define AR724X_DDR_DIV_MASK             0x3
175
176#define AR7242_PLL_REG_ETH0_INT_CLOCK   0x2c
177
178#define AR91XX_PLL_REG_CPU_CONFIG       0x00
179#define AR91XX_PLL_REG_ETH_CONFIG       0x04
180#define AR91XX_PLL_REG_ETH0_INT_CLOCK   0x14
181#define AR91XX_PLL_REG_ETH1_INT_CLOCK   0x18
182
183#define AR91XX_PLL_DIV_SHIFT            0
184#define AR91XX_PLL_DIV_MASK             0x3ff
185#define AR91XX_DDR_DIV_SHIFT            22
186#define AR91XX_DDR_DIV_MASK             0x3
187#define AR91XX_AHB_DIV_SHIFT            19
188#define AR91XX_AHB_DIV_MASK             0x1
189
190#define AR91XX_ETH0_PLL_SHIFT           20
191#define AR91XX_ETH1_PLL_SHIFT           22
192
193#define AR933X_PLL_CPU_CONFIG_REG       0x00
194#define AR933X_PLL_CLOCK_CTRL_REG       0x08
195
196#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT        10
197#define AR933X_PLL_CPU_CONFIG_NINT_MASK         0x3f
198#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT      16
199#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
200#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT      23
201#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK       0x7
202
203#define AR933X_PLL_CLOCK_CTRL_BYPASS            BIT(2)
204#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT     5
205#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK      0x3
206#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT     10
207#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK      0x3
208#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT     15
209#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK      0x7
210
211#define AR934X_PLL_REG_CPU_CONFIG       0x00
212#define AR934X_PLL_REG_DDR_CTRL_CLOCK   0x8
213
214#define AR934X_CPU_PLL_CFG_OUTDIV_MSB   21
215#define AR934X_CPU_PLL_CFG_OUTDIV_LSB   19
216#define AR934X_CPU_PLL_CFG_OUTDIV_MASK  0x00380000
217
218#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x)                \
219        (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >>      \
220        AR934X_CPU_PLL_CFG_OUTDIV_LSB)
221
222#define AR934X_DDR_PLL_CFG_OUTDIV_MSB   25
223#define AR934X_DDR_PLL_CFG_OUTDIV_LSB   23
224#define AR934X_DDR_PLL_CFG_OUTDIV_MASK  0x03800000
225
226#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x)                \
227        (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >>      \
228        AR934X_DDR_PLL_CFG_OUTDIV_LSB)
229
230#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x)                \
231        (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) &       \
232        AR934X_DDR_PLL_CFG_OUTDIV_MASK)
233
234#define AR934X_CPU_PLL_CFG_REFDIV_MSB   16
235#define AR934X_CPU_PLL_CFG_REFDIV_LSB   12
236#define AR934X_CPU_PLL_CFG_REFDIV_MASK  0x0001f000
237
238#define AR934X_CPU_PLL_CFG_REFDIV_GET(x)                \
239        (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >>      \
240        AR934X_CPU_PLL_CFG_REFDIV_LSB)
241
242#define AR934X_CPU_PLL_CFG_REFDIV_SET(x)                \
243        (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) &       \
244        AR934X_CPU_PLL_CFG_REFDIV_MASK)
245
246#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2
247
248#define AR934X_CPU_PLL_CFG_NINT_MSB     11
249#define AR934X_CPU_PLL_CFG_NINT_LSB     6
250#define AR934X_CPU_PLL_CFG_NINT_MASK    0x00000fc0
251
252#define AR934X_CPU_PLL_CFG_NINT_GET(x)                  \
253        (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >>        \
254        AR934X_CPU_PLL_CFG_NINT_LSB)
255
256#define AR934X_CPU_PLL_CFG_NINT_SET(x)                  \
257        (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) &         \
258        AR934X_CPU_PLL_CFG_NINT_MASK)
259
260#define AR934X_CPU_PLL_CFG_NINT_RESET   20
261
262#define AR934X_CPU_PLL_CFG_NFRAC_MSB    5
263#define AR934X_CPU_PLL_CFG_NFRAC_LSB    0
264#define AR934X_CPU_PLL_CFG_NFRAC_MASK   0x0000003f
265
266#define AR934X_CPU_PLL_CFG_NFRAC_GET(x)         \
267        (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >>       \
268        AR934X_CPU_PLL_CFG_NFRAC_LSB)
269
270#define AR934X_CPU_PLL_CFG_NFRAC_SET(x)         \
271        (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) &        \
272        AR934X_CPU_PLL_CFG_NFRAC_MASK)
273
274#define AR934X_DDR_PLL_CFG_REFDIV_MSB   20
275#define AR934X_DDR_PLL_CFG_REFDIV_LSB   16
276#define AR934X_DDR_PLL_CFG_REFDIV_MASK  0x001f0000
277
278#define AR934X_DDR_PLL_CFG_REFDIV_GET(x)                \
279        (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >>      \
280        AR934X_DDR_PLL_CFG_REFDIV_LSB)
281
282#define AR934X_DDR_PLL_CFG_REFDIV_SET(x)                \
283        (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) &       \
284        AR934X_DDR_PLL_CFG_REFDIV_MASK)
285
286#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2
287
288#define AR934X_DDR_PLL_CFG_NINT_MSB     15
289#define AR934X_DDR_PLL_CFG_NINT_LSB     10
290#define AR934X_DDR_PLL_CFG_NINT_MASK    0x0000fc00
291
292#define AR934X_DDR_PLL_CFG_NINT_GET(x)                  \
293        (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >>        \
294        AR934X_DDR_PLL_CFG_NINT_LSB)
295
296#define AR934X_DDR_PLL_CFG_NINT_SET(x)                  \
297        (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) &         \
298        AR934X_DDR_PLL_CFG_NINT_MASK)
299
300#define AR934X_DDR_PLL_CFG_NINT_RESET   20
301
302#define AR934X_DDR_PLL_CFG_NFRAC_MSB    9
303#define AR934X_DDR_PLL_CFG_NFRAC_LSB    0
304#define AR934X_DDR_PLL_CFG_NFRAC_MASK   0x000003ff
305
306#define AR934X_DDR_PLL_CFG_NFRAC_GET(x)         \
307        (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >>       \
308        AR934X_DDR_PLL_CFG_NFRAC_LSB)
309
310#define AR934X_DDR_PLL_CFG_NFRAC_SET(x)         \
311        (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) &        \
312        AR934X_DDR_PLL_CFG_NFRAC_MASK)
313
314#define AR934X_DDR_PLL_CFG_NFRAC_RESET  512
315
316#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB        19
317#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB        15
318#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK       0x000f8000
319
320#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x)             \
321        (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >>   \
322        AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB)
323
324#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x)             \
325        (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) &    \
326        AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
327
328#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET              0
329
330#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB        14
331#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB        10
332#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK       0x00007c00
333
334#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x)             \
335        (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >>   \
336        AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB)
337
338#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x)             \
339        (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) &    \
340        AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
341
342#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET      0
343
344#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB        9
345#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB        5
346#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK       0x000003e0
347
348#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x)             \
349        (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >>   \
350        AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB)
351
352#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x)             \
353        (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) &    \
354        AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
355
356#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET      0
357
358#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB  24
359#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB  24
360#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
361
362#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x)       \
363        (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \
364        AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB)
365
366#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x)       \
367        (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \
368        AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
369
370#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET        1
371
372extern void __iomem *ar71xx_pll_base;
373
374static inline void ar71xx_pll_wr(unsigned reg, u32 val)
375{
376        __raw_writel(val, ar71xx_pll_base + reg);
377}
378
379static inline u32 ar71xx_pll_rr(unsigned reg)
380{
381        return __raw_readl(ar71xx_pll_base + reg);
382}
383
384/*
385 * USB_CONFIG block
386 */
387#define USB_CTRL_REG_FLADJ      0x00
388#define USB_CTRL_REG_CONFIG     0x04
389
390extern void __iomem *ar71xx_usb_ctrl_base;
391
392static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
393{
394        __raw_writel(val, ar71xx_usb_ctrl_base + reg);
395}
396
397static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
398{
399        return __raw_readl(ar71xx_usb_ctrl_base + reg);
400}
401
402/*
403 * GPIO block
404 */
405#define GPIO_REG_OE             0x00
406#define GPIO_REG_IN             0x04
407#define GPIO_REG_OUT            0x08
408#define GPIO_REG_SET            0x0c
409#define GPIO_REG_CLEAR          0x10
410#define GPIO_REG_INT_MODE       0x14
411#define GPIO_REG_INT_TYPE       0x18
412#define GPIO_REG_INT_POLARITY   0x1c
413#define GPIO_REG_INT_PENDING    0x20
414#define GPIO_REG_INT_ENABLE     0x24
415#define GPIO_REG_FUNC           0x28
416
417#define AR71XX_GPIO_FUNC_STEREO_EN      BIT(17)
418#define AR71XX_GPIO_FUNC_SLIC_EN        BIT(16)
419#define AR71XX_GPIO_FUNC_SPI_CS2_EN     BIT(13)
420#define AR71XX_GPIO_FUNC_SPI_CS1_EN     BIT(12)
421#define AR71XX_GPIO_FUNC_UART_EN        BIT(8)
422#define AR71XX_GPIO_FUNC_USB_OC_EN      BIT(4)
423#define AR71XX_GPIO_FUNC_USB_CLK_EN     BIT(0)
424
425#define AR71XX_GPIO_COUNT       16
426
427#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN         BIT(19)
428#define AR724X_GPIO_FUNC_SPI_EN                 BIT(18)
429#define AR724X_GPIO_FUNC_SPI_CS_EN2             BIT(14)
430#define AR724X_GPIO_FUNC_SPI_CS_EN1             BIT(13)
431#define AR724X_GPIO_FUNC_CLK_OBS5_EN            BIT(12)
432#define AR724X_GPIO_FUNC_CLK_OBS4_EN            BIT(11)
433#define AR724X_GPIO_FUNC_CLK_OBS3_EN            BIT(10)
434#define AR724X_GPIO_FUNC_CLK_OBS2_EN            BIT(9)
435#define AR724X_GPIO_FUNC_CLK_OBS1_EN            BIT(8)
436#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN     BIT(7)
437#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN     BIT(6)
438#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN     BIT(5)
439#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN     BIT(4)
440#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN     BIT(3)
441#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN        BIT(2)
442#define AR724X_GPIO_FUNC_UART_EN                BIT(1)
443#define AR724X_GPIO_FUNC_JTAG_DISABLE           BIT(0)
444
445#define AR724X_GPIO_COUNT       18
446
447#define AR91XX_GPIO_FUNC_WMAC_LED_EN    BIT(22)
448#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
449#define AR91XX_GPIO_FUNC_I2S_REFCLKEN   BIT(20)
450#define AR91XX_GPIO_FUNC_I2S_MCKEN      BIT(19)
451#define AR91XX_GPIO_FUNC_I2S1_EN        BIT(18)
452#define AR91XX_GPIO_FUNC_I2S0_EN        BIT(17)
453#define AR91XX_GPIO_FUNC_SLIC_EN        BIT(16)
454#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
455#define AR91XX_GPIO_FUNC_UART_EN        BIT(8)
456#define AR91XX_GPIO_FUNC_USB_CLK_EN     BIT(4)
457
458#define AR91XX_GPIO_COUNT       22
459
460#define AR933X_GPIO_COUNT       30
461
462#define AR934X_GPIO_FUNC_SPI_CS_1_EN    BIT(14)
463#define AR934X_GPIO_FUNC_SPI_CS_0_EN    BIT(13)
464
465#define AR934X_GPIO_COUNT               32
466#define AR934X_GPIO_FUNC_DDR_DQOE_EN    BIT(17)
467
468extern void __iomem *ar71xx_gpio_base;
469
470static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
471{
472        __raw_writel(value, ar71xx_gpio_base + reg);
473}
474
475static inline u32 ar71xx_gpio_rr(unsigned reg)
476{
477        return __raw_readl(ar71xx_gpio_base + reg);
478}
479
480void ar71xx_gpio_init(void) __init;
481void ar71xx_gpio_function_enable(u32 mask);
482void ar71xx_gpio_function_disable(u32 mask);
483void ar71xx_gpio_function_setup(u32 set, u32 clear);
484
485/*
486 * DDR_CTRL block
487 */
488#define AR71XX_DDR_REG_PCI_WIN0         0x7c
489#define AR71XX_DDR_REG_PCI_WIN1         0x80
490#define AR71XX_DDR_REG_PCI_WIN2         0x84
491#define AR71XX_DDR_REG_PCI_WIN3         0x88
492#define AR71XX_DDR_REG_PCI_WIN4         0x8c
493#define AR71XX_DDR_REG_PCI_WIN5         0x90
494#define AR71XX_DDR_REG_PCI_WIN6         0x94
495#define AR71XX_DDR_REG_PCI_WIN7         0x98
496#define AR71XX_DDR_REG_FLUSH_GE0        0x9c
497#define AR71XX_DDR_REG_FLUSH_GE1        0xa0
498#define AR71XX_DDR_REG_FLUSH_USB        0xa4
499#define AR71XX_DDR_REG_FLUSH_PCI        0xa8
500
501#define AR724X_DDR_REG_FLUSH_GE0        0x7c
502#define AR724X_DDR_REG_FLUSH_GE1        0x80
503#define AR724X_DDR_REG_FLUSH_USB        0x84
504#define AR724X_DDR_REG_FLUSH_PCIE       0x88
505
506#define AR91XX_DDR_REG_FLUSH_GE0        0x7c
507#define AR91XX_DDR_REG_FLUSH_GE1        0x80
508#define AR91XX_DDR_REG_FLUSH_USB        0x84
509#define AR91XX_DDR_REG_FLUSH_WMAC       0x88
510
511#define AR933X_DDR_REG_FLUSH_GE0        0x7c
512#define AR933X_DDR_REG_FLUSH_GE1        0x80
513#define AR933X_DDR_REG_FLUSH_USB        0x84
514#define AR933X_DDR_REG_FLUSH_WMAC       0x88
515
516#define AR934X_DDR_REG_FLUSH_GE0        0x9c
517#define AR934X_DDR_REG_FLUSH_GE1        0xa0
518#define AR934X_DDR_REG_FLUSH_USB        0xa4
519#define AR934X_DDR_REG_FLUSH_PCIE       0xa8
520
521
522#define PCI_WIN0_OFFS   0x10000000
523#define PCI_WIN1_OFFS   0x11000000
524#define PCI_WIN2_OFFS   0x12000000
525#define PCI_WIN3_OFFS   0x13000000
526#define PCI_WIN4_OFFS   0x14000000
527#define PCI_WIN5_OFFS   0x15000000
528#define PCI_WIN6_OFFS   0x16000000
529#define PCI_WIN7_OFFS   0x07000000
530
531extern void __iomem *ar71xx_ddr_base;
532
533static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
534{
535        __raw_writel(val, ar71xx_ddr_base + reg);
536}
537
538static inline u32 ar71xx_ddr_rr(unsigned reg)
539{
540        return __raw_readl(ar71xx_ddr_base + reg);
541}
542
543void ar71xx_ddr_flush(u32 reg);
544
545/*
546 * PCI block
547 */
548#define AR71XX_PCI_CFG_BASE     (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
549#define AR71XX_PCI_CFG_SIZE     0x100
550
551#define PCI_REG_CRP_AD_CBE      0x00
552#define PCI_REG_CRP_WRDATA      0x04
553#define PCI_REG_CRP_RDDATA      0x08
554#define PCI_REG_CFG_AD          0x0c
555#define PCI_REG_CFG_CBE         0x10
556#define PCI_REG_CFG_WRDATA      0x14
557#define PCI_REG_CFG_RDDATA      0x18
558#define PCI_REG_PCI_ERR         0x1c
559#define PCI_REG_PCI_ERR_ADDR    0x20
560#define PCI_REG_AHB_ERR         0x24
561#define PCI_REG_AHB_ERR_ADDR    0x28
562
563#define PCI_CRP_CMD_WRITE       0x00010000
564#define PCI_CRP_CMD_READ        0x00000000
565#define PCI_CFG_CMD_READ        0x0000000a
566#define PCI_CFG_CMD_WRITE       0x0000000b
567
568#define PCI_IDSEL_ADL_START     17
569
570#define AR724X_PCI_CFG_BASE     (AR71XX_PCI_MEM_BASE + 0x4000000)
571#define AR724X_PCI_CFG_SIZE     0x1000
572
573#define AR724X_PCI_REG_APP              0x00
574#define AR724X_PCI_REG_RESET            0x18
575#define AR724X_PCI_REG_INT_STATUS       0x4c
576#define AR724X_PCI_REG_INT_MASK         0x50
577
578#define AR724X_PCI_APP_LTSSM_ENABLE     BIT(0)
579#define AR724X_PCI_RESET_LINK_UP        BIT(0)
580
581#define AR724X_PCI_INT_DEV0             BIT(14)
582
583/*
584 * RESET block
585 */
586#define AR71XX_RESET_REG_TIMER                  0x00
587#define AR71XX_RESET_REG_TIMER_RELOAD           0x04
588#define AR71XX_RESET_REG_WDOG_CTRL              0x08
589#define AR71XX_RESET_REG_WDOG                   0x0c
590#define AR71XX_RESET_REG_MISC_INT_STATUS        0x10
591#define AR71XX_RESET_REG_MISC_INT_ENABLE        0x14
592#define AR71XX_RESET_REG_PCI_INT_STATUS         0x18
593#define AR71XX_RESET_REG_PCI_INT_ENABLE         0x1c
594#define AR71XX_RESET_REG_GLOBAL_INT_STATUS      0x20
595#define AR71XX_RESET_REG_RESET_MODULE           0x24
596#define AR71XX_RESET_REG_PERFC_CTRL             0x2c
597#define AR71XX_RESET_REG_PERFC0                 0x30
598#define AR71XX_RESET_REG_PERFC1                 0x34
599#define AR71XX_RESET_REG_REV_ID                 0x90
600
601#define AR91XX_RESET_REG_GLOBAL_INT_STATUS      0x18
602#define AR91XX_RESET_REG_RESET_MODULE           0x1c
603#define AR91XX_RESET_REG_PERF_CTRL              0x20
604#define AR91XX_RESET_REG_PERFC0                 0x24
605#define AR91XX_RESET_REG_PERFC1                 0x28
606
607#define AR724X_RESET_REG_RESET_MODULE           0x1c
608
609#define AR933X_RESET_REG_RESET_MODULE           0x1c
610#define AR933X_RESET_REG_BOOTSTRAP              0xac
611#define AR933X_BOOTSTRAP_REF_CLK_40             BIT(0)
612
613#define AR934X_RESET_REG_RESET_MODULE           0x1c
614#define AR934X_RESET_REG_BOOTSTRAP              0xb0
615/* 0 - 25MHz   1 - 40 MHz */
616#define AR934X_REF_CLK_40                       (1 << 4)
617
618#define WDOG_CTRL_LAST_RESET            BIT(31)
619#define WDOG_CTRL_ACTION_MASK           3
620#define WDOG_CTRL_ACTION_NONE           0       /* no action */
621#define WDOG_CTRL_ACTION_GPI            1       /* general purpose interrupt */
622#define WDOG_CTRL_ACTION_NMI            2       /* NMI */
623#define WDOG_CTRL_ACTION_FCR            3       /* full chip reset */
624
625#define MISC_INT_ENET_LINK              BIT(12)
626#define MISC_INT_DDR_PERF               BIT(11)
627#define MISC_INT_TIMER4         BIT(10)
628#define MISC_INT_TIMER3         BIT(9)
629#define MISC_INT_TIMER2         BIT(8)
630#define MISC_INT_DMA                    BIT(7)
631#define MISC_INT_OHCI                   BIT(6)
632#define MISC_INT_PERFC                  BIT(5)
633#define MISC_INT_WDOG                   BIT(4)
634#define MISC_INT_UART                   BIT(3)
635#define MISC_INT_GPIO                   BIT(2)
636#define MISC_INT_ERROR                  BIT(1)
637#define MISC_INT_TIMER                  BIT(0)
638
639#define PCI_INT_CORE                    BIT(4)
640#define PCI_INT_DEV2                    BIT(2)
641#define PCI_INT_DEV1                    BIT(1)
642#define PCI_INT_DEV0                    BIT(0)
643
644#define RESET_MODULE_EXTERNAL           BIT(28)
645#define RESET_MODULE_FULL_CHIP          BIT(24)
646#define RESET_MODULE_AMBA2WMAC          BIT(22)
647#define RESET_MODULE_CPU_NMI            BIT(21)
648#define RESET_MODULE_CPU_COLD           BIT(20)
649#define RESET_MODULE_DMA                BIT(19)
650#define RESET_MODULE_SLIC               BIT(18)
651#define RESET_MODULE_STEREO             BIT(17)
652#define RESET_MODULE_DDR                BIT(16)
653#define RESET_MODULE_GE1_MAC            BIT(13)
654#define RESET_MODULE_GE1_PHY            BIT(12)
655#define RESET_MODULE_USBSUS_OVERRIDE    BIT(10)
656#define RESET_MODULE_GE0_MAC            BIT(9)
657#define RESET_MODULE_GE0_PHY            BIT(8)
658#define RESET_MODULE_USB_OHCI_DLL       BIT(6)
659#define RESET_MODULE_USB_HOST           BIT(5)
660#define RESET_MODULE_USB_PHY            BIT(4)
661#define RESET_MODULE_USB_OHCI_DLL_7240  BIT(3)
662#define RESET_MODULE_PCI_BUS            BIT(1)
663#define RESET_MODULE_PCI_CORE           BIT(0)
664
665#define AR724X_RESET_GE1_MDIO           BIT(23)
666#define AR724X_RESET_GE0_MDIO           BIT(22)
667#define AR724X_RESET_PCIE_PHY_SERIAL    BIT(10)
668#define AR724X_RESET_PCIE_PHY           BIT(7)
669#define AR724X_RESET_PCIE               BIT(6)
670#define AR724X_RESET_USB_HOST           BIT(5)
671#define AR724X_RESET_USB_PHY            BIT(4)
672#define AR724X_RESET_USBSUS_OVERRIDE    BIT(3)
673
674#define AR933X_RESET_GE1_MDIO           BIT(23)
675#define AR933X_RESET_GE0_MDIO           BIT(22)
676#define AR933X_RESET_GE1_MAC            BIT(13)
677#define AR933X_RESET_GE0_MAC            BIT(9)
678
679#define REV_ID_MAJOR_MASK       0xfff0
680#define REV_ID_MAJOR_AR71XX     0x00a0
681#define REV_ID_MAJOR_AR913X     0x00b0
682#define REV_ID_MAJOR_AR7240     0x00c0
683#define REV_ID_MAJOR_AR7241     0x0100
684#define REV_ID_MAJOR_AR7242     0x1100
685#define REV_ID_MAJOR_AR9330     0x0110
686#define REV_ID_MAJOR_AR9331     0x1110
687#define REV_ID_MAJOR_AR9341     0x0120
688#define REV_ID_MAJOR_AR9342     0x1120
689#define REV_ID_MAJOR_AR9344     0x2120
690
691#define AR71XX_REV_ID_MINOR_MASK        0x3
692#define AR71XX_REV_ID_MINOR_AR7130      0x0
693#define AR71XX_REV_ID_MINOR_AR7141      0x1
694#define AR71XX_REV_ID_MINOR_AR7161      0x2
695#define AR71XX_REV_ID_REVISION_MASK     0x3
696#define AR71XX_REV_ID_REVISION_SHIFT    2
697
698#define AR91XX_REV_ID_MINOR_MASK        0x3
699#define AR91XX_REV_ID_MINOR_AR9130      0x0
700#define AR91XX_REV_ID_MINOR_AR9132      0x1
701#define AR91XX_REV_ID_REVISION_MASK     0x3
702#define AR91XX_REV_ID_REVISION_SHIFT    2
703
704#define AR724X_REV_ID_REVISION_MASK     0x3
705
706#define AR933X_REV_ID_REVISION_MASK     0xf
707
708#define AR934X_REV_ID_REVISION_MASK     0xf
709
710extern void __iomem *ar71xx_reset_base;
711
712static inline void ar71xx_reset_wr(unsigned reg, u32 val)
713{
714        __raw_writel(val, ar71xx_reset_base + reg);
715}
716
717static inline u32 ar71xx_reset_rr(unsigned reg)
718{
719        return __raw_readl(ar71xx_reset_base + reg);
720}
721
722void ar71xx_device_stop(u32 mask);
723void ar71xx_device_start(u32 mask);
724int ar71xx_device_stopped(u32 mask);
725
726/*
727 * SPI block
728 */
729#define SPI_REG_FS              0x00    /* Function Select */
730#define SPI_REG_CTRL            0x04    /* SPI Control */
731#define SPI_REG_IOC             0x08    /* SPI I/O Control */
732#define SPI_REG_RDS             0x0c    /* Read Data Shift */
733
734#define SPI_FS_GPIO             BIT(0)  /* Enable GPIO mode */
735
736#define SPI_CTRL_RD             BIT(6)  /* Remap Disable */
737#define SPI_CTRL_DIV_MASK       0x3f
738
739#define SPI_IOC_DO              BIT(0)  /* Data Out pin */
740#define SPI_IOC_CLK             BIT(8)  /* CLK pin */
741#define SPI_IOC_CS(n)           BIT(16 + (n))
742#define SPI_IOC_CS0             SPI_IOC_CS(0)
743#define SPI_IOC_CS1             SPI_IOC_CS(1)
744#define SPI_IOC_CS2             SPI_IOC_CS(2)
745#define SPI_IOC_CS_ALL          (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
746
747void ar71xx_flash_acquire(void);
748void ar71xx_flash_release(void);
749
750/*
751 * MII_CTRL block
752 */
753#define MII_REG_MII0_CTRL       0x00
754#define MII_REG_MII1_CTRL       0x04
755
756#define MII0_CTRL_IF_GMII       0
757#define MII0_CTRL_IF_MII        1
758#define MII0_CTRL_IF_RGMII      2
759#define MII0_CTRL_IF_RMII       3
760
761#define MII1_CTRL_IF_RGMII      0
762#define MII1_CTRL_IF_RMII       1
763
764#endif /* __ASSEMBLER__ */
765
766#endif /* __ASM_MACH_AR71XX_H */
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