source: trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @ 29010

Last change on this file since 29010 was 29010, checked in by juhosg, 4 years ago

ar71xx: configure MII interface type from ar71xx_setup_phy_if_mode

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1/*
2 *  Atheros AR71xx SoC specific definitions
3 *
4 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 *  Parts of this file are based on Atheros 2.6.15 BSP
9 *  Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 *  This program is free software; you can redistribute it and/or modify it
12 *  under the terms of the GNU General Public License version 2 as published
13 *  by the Free Software Foundation.
14 */
15
16#ifndef __ASM_MACH_AR71XX_H
17#define __ASM_MACH_AR71XX_H
18
19#include <linux/types.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/bitops.h>
23
24#ifndef __ASSEMBLER__
25
26#define AR71XX_PCI_MEM_BASE     0x10000000
27#define AR71XX_PCI_MEM_SIZE     0x08000000
28#define AR71XX_APB_BASE         0x18000000
29#define AR71XX_GE0_BASE         0x19000000
30#define AR71XX_GE0_SIZE         0x01000000
31#define AR71XX_GE1_BASE         0x1a000000
32#define AR71XX_GE1_SIZE         0x01000000
33#define AR71XX_EHCI_BASE        0x1b000000
34#define AR71XX_EHCI_SIZE        0x01000000
35#define AR71XX_OHCI_BASE        0x1c000000
36#define AR71XX_OHCI_SIZE        0x01000000
37#define AR7240_OHCI_BASE        0x1b000000
38#define AR7240_OHCI_SIZE        0x01000000
39#define AR71XX_SPI_BASE         0x1f000000
40#define AR71XX_SPI_SIZE         0x01000000
41
42#define AR71XX_DDR_CTRL_BASE    (AR71XX_APB_BASE + 0x00000000)
43#define AR71XX_DDR_CTRL_SIZE    0x10000
44#define AR71XX_CPU_BASE         (AR71XX_APB_BASE + 0x00010000)
45#define AR71XX_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
46#define AR71XX_UART_SIZE        0x10000
47#define AR71XX_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
48#define AR71XX_USB_CTRL_SIZE    0x10000
49#define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
50#define AR71XX_GPIO_SIZE        0x10000
51#define AR71XX_PLL_BASE         (AR71XX_APB_BASE + 0x00050000)
52#define AR71XX_PLL_SIZE         0x10000
53#define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
54#define AR71XX_RESET_SIZE       0x10000
55#define AR71XX_MII_BASE         (AR71XX_APB_BASE + 0x00070000)
56#define AR71XX_MII_SIZE         0x10000
57#define AR71XX_SLIC_BASE        (AR71XX_APB_BASE + 0x00090000)
58#define AR71XX_SLIC_SIZE        0x10000
59#define AR71XX_DMA_BASE         (AR71XX_APB_BASE + 0x000A0000)
60#define AR71XX_DMA_SIZE         0x10000
61#define AR71XX_STEREO_BASE      (AR71XX_APB_BASE + 0x000B0000)
62#define AR71XX_STEREO_SIZE      0x10000
63
64#define AR724X_PCI_CRP_BASE     (AR71XX_APB_BASE + 0x000C0000)
65#define AR724X_PCI_CRP_SIZE     0x100
66
67#define AR724X_PCI_CTRL_BASE    (AR71XX_APB_BASE + 0x000F0000)
68#define AR724X_PCI_CTRL_SIZE    0x100
69
70#define AR91XX_WMAC_BASE        (AR71XX_APB_BASE + 0x000C0000)
71#define AR91XX_WMAC_SIZE        0x30000
72
73#define AR933X_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
74#define AR933X_UART_SIZE        0x14
75#define AR933X_GMAC_BASE        (AR71XX_APB_BASE + 0x00070000)
76#define AR933X_GMAC_SIZE        0x04
77#define AR933X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
78#define AR933X_WMAC_SIZE        0x20000
79
80#define AR934X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
81#define AR934X_WMAC_SIZE        0x20000
82
83#define AR71XX_MEM_SIZE_MIN     0x0200000
84#define AR71XX_MEM_SIZE_MAX     0x10000000
85
86#define AR71XX_CPU_IRQ_BASE     0
87#define AR71XX_MISC_IRQ_BASE    8
88#define AR71XX_MISC_IRQ_COUNT   32
89#define AR71XX_GPIO_IRQ_BASE    40
90#define AR71XX_GPIO_IRQ_COUNT   32
91#define AR71XX_PCI_IRQ_BASE     72
92#define AR71XX_PCI_IRQ_COUNT    8
93
94#define AR71XX_CPU_IRQ_IP2      (AR71XX_CPU_IRQ_BASE + 2)
95#define AR71XX_CPU_IRQ_USB      (AR71XX_CPU_IRQ_BASE + 3)
96#define AR71XX_CPU_IRQ_GE0      (AR71XX_CPU_IRQ_BASE + 4)
97#define AR71XX_CPU_IRQ_GE1      (AR71XX_CPU_IRQ_BASE + 5)
98#define AR71XX_CPU_IRQ_MISC     (AR71XX_CPU_IRQ_BASE + 6)
99#define AR71XX_CPU_IRQ_TIMER    (AR71XX_CPU_IRQ_BASE + 7)
100
101#define AR71XX_MISC_IRQ_TIMER   (AR71XX_MISC_IRQ_BASE + 0)
102#define AR71XX_MISC_IRQ_ERROR   (AR71XX_MISC_IRQ_BASE + 1)
103#define AR71XX_MISC_IRQ_GPIO    (AR71XX_MISC_IRQ_BASE + 2)
104#define AR71XX_MISC_IRQ_UART    (AR71XX_MISC_IRQ_BASE + 3)
105#define AR71XX_MISC_IRQ_WDOG    (AR71XX_MISC_IRQ_BASE + 4)
106#define AR71XX_MISC_IRQ_PERFC   (AR71XX_MISC_IRQ_BASE + 5)
107#define AR71XX_MISC_IRQ_OHCI    (AR71XX_MISC_IRQ_BASE + 6)
108#define AR71XX_MISC_IRQ_DMA     (AR71XX_MISC_IRQ_BASE + 7)
109#define AR71XX_MISC_IRQ_TIMER2  (AR71XX_MISC_IRQ_BASE + 8)
110#define AR71XX_MISC_IRQ_TIMER3  (AR71XX_MISC_IRQ_BASE + 9)
111#define AR71XX_MISC_IRQ_TIMER4  (AR71XX_MISC_IRQ_BASE + 10)
112#define AR71XX_MISC_IRQ_DDR_PERF        (AR71XX_MISC_IRQ_BASE + 11)
113#define AR71XX_MISC_IRQ_ENET_LINK       (AR71XX_MISC_IRQ_BASE + 12)
114
115#define AR71XX_GPIO_IRQ(_x)     (AR71XX_GPIO_IRQ_BASE + (_x))
116
117#define AR71XX_PCI_IRQ_DEV0     (AR71XX_PCI_IRQ_BASE + 0)
118#define AR71XX_PCI_IRQ_DEV1     (AR71XX_PCI_IRQ_BASE + 1)
119#define AR71XX_PCI_IRQ_DEV2     (AR71XX_PCI_IRQ_BASE + 2)
120#define AR71XX_PCI_IRQ_CORE     (AR71XX_PCI_IRQ_BASE + 4)
121
122extern u32 ar71xx_ahb_freq;
123extern u32 ar71xx_cpu_freq;
124extern u32 ar71xx_ddr_freq;
125extern u32 ar71xx_ref_freq;
126
127enum ar71xx_soc_type {
128        AR71XX_SOC_UNKNOWN,
129        AR71XX_SOC_AR7130,
130        AR71XX_SOC_AR7141,
131        AR71XX_SOC_AR7161,
132        AR71XX_SOC_AR7240,
133        AR71XX_SOC_AR7241,
134        AR71XX_SOC_AR7242,
135        AR71XX_SOC_AR9130,
136        AR71XX_SOC_AR9132,
137        AR71XX_SOC_AR9330,
138        AR71XX_SOC_AR9331,
139        AR71XX_SOC_AR9341,
140        AR71XX_SOC_AR9342,
141        AR71XX_SOC_AR9344,
142};
143extern u32 ar71xx_soc_rev;
144
145extern enum ar71xx_soc_type ar71xx_soc;
146
147/*
148 * PLL block
149 */
150#define AR71XX_PLL_REG_CPU_CONFIG       0x00
151#define AR71XX_PLL_REG_SEC_CONFIG       0x04
152#define AR71XX_PLL_REG_ETH0_INT_CLOCK   0x10
153#define AR71XX_PLL_REG_ETH1_INT_CLOCK   0x14
154
155#define AR71XX_PLL_DIV_SHIFT            3
156#define AR71XX_PLL_DIV_MASK             0x1f
157#define AR71XX_CPU_DIV_SHIFT            16
158#define AR71XX_CPU_DIV_MASK             0x3
159#define AR71XX_DDR_DIV_SHIFT            18
160#define AR71XX_DDR_DIV_MASK             0x3
161#define AR71XX_AHB_DIV_SHIFT            20
162#define AR71XX_AHB_DIV_MASK             0x7
163
164#define AR71XX_ETH0_PLL_SHIFT           17
165#define AR71XX_ETH1_PLL_SHIFT           19
166
167#define AR724X_PLL_REG_CPU_CONFIG       0x00
168#define AR724X_PLL_REG_PCIE_CONFIG      0x18
169
170#define AR724X_PLL_DIV_SHIFT            0
171#define AR724X_PLL_DIV_MASK             0x3ff
172#define AR724X_PLL_REF_DIV_SHIFT        10
173#define AR724X_PLL_REF_DIV_MASK         0xf
174#define AR724X_AHB_DIV_SHIFT            19
175#define AR724X_AHB_DIV_MASK             0x1
176#define AR724X_DDR_DIV_SHIFT            22
177#define AR724X_DDR_DIV_MASK             0x3
178
179#define AR7242_PLL_REG_ETH0_INT_CLOCK   0x2c
180
181#define AR91XX_PLL_REG_CPU_CONFIG       0x00
182#define AR91XX_PLL_REG_ETH_CONFIG       0x04
183#define AR91XX_PLL_REG_ETH0_INT_CLOCK   0x14
184#define AR91XX_PLL_REG_ETH1_INT_CLOCK   0x18
185
186#define AR91XX_PLL_DIV_SHIFT            0
187#define AR91XX_PLL_DIV_MASK             0x3ff
188#define AR91XX_DDR_DIV_SHIFT            22
189#define AR91XX_DDR_DIV_MASK             0x3
190#define AR91XX_AHB_DIV_SHIFT            19
191#define AR91XX_AHB_DIV_MASK             0x1
192
193#define AR91XX_ETH0_PLL_SHIFT           20
194#define AR91XX_ETH1_PLL_SHIFT           22
195
196#define AR933X_PLL_CPU_CONFIG_REG       0x00
197#define AR933X_PLL_CLOCK_CTRL_REG       0x08
198
199#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT        10
200#define AR933X_PLL_CPU_CONFIG_NINT_MASK         0x3f
201#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT      16
202#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
203#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT      23
204#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK       0x7
205
206#define AR933X_PLL_CLOCK_CTRL_BYPASS            BIT(2)
207#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT     5
208#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK      0x3
209#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT     10
210#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK      0x3
211#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT     15
212#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK      0x7
213
214#define AR934X_PLL_REG_CPU_CONFIG       0x00
215#define AR934X_PLL_REG_DDR_CONFIG       0x04
216#define AR934X_PLL_REG_DDR_CTRL_CLOCK   0x8
217
218#define AR934X_CPU_PLL_CFG_OUTDIV_MSB   21
219#define AR934X_CPU_PLL_CFG_OUTDIV_LSB   19
220#define AR934X_CPU_PLL_CFG_OUTDIV_MASK  0x00380000
221
222#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x)                \
223        (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >>      \
224        AR934X_CPU_PLL_CFG_OUTDIV_LSB)
225
226#define AR934X_DDR_PLL_CFG_OUTDIV_MSB   25
227#define AR934X_DDR_PLL_CFG_OUTDIV_LSB   23
228#define AR934X_DDR_PLL_CFG_OUTDIV_MASK  0x03800000
229
230#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x)                \
231        (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >>      \
232        AR934X_DDR_PLL_CFG_OUTDIV_LSB)
233
234#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x)                \
235        (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) &       \
236        AR934X_DDR_PLL_CFG_OUTDIV_MASK)
237
238#define AR934X_CPU_PLL_CFG_REFDIV_MSB   16
239#define AR934X_CPU_PLL_CFG_REFDIV_LSB   12
240#define AR934X_CPU_PLL_CFG_REFDIV_MASK  0x0001f000
241
242#define AR934X_CPU_PLL_CFG_REFDIV_GET(x)                \
243        (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >>      \
244        AR934X_CPU_PLL_CFG_REFDIV_LSB)
245
246#define AR934X_CPU_PLL_CFG_REFDIV_SET(x)                \
247        (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) &       \
248        AR934X_CPU_PLL_CFG_REFDIV_MASK)
249
250#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2
251
252#define AR934X_CPU_PLL_CFG_NINT_MSB     11
253#define AR934X_CPU_PLL_CFG_NINT_LSB     6
254#define AR934X_CPU_PLL_CFG_NINT_MASK    0x00000fc0
255
256#define AR934X_CPU_PLL_CFG_NINT_GET(x)                  \
257        (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >>        \
258        AR934X_CPU_PLL_CFG_NINT_LSB)
259
260#define AR934X_CPU_PLL_CFG_NINT_SET(x)                  \
261        (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) &         \
262        AR934X_CPU_PLL_CFG_NINT_MASK)
263
264#define AR934X_CPU_PLL_CFG_NINT_RESET   20
265
266#define AR934X_CPU_PLL_CFG_NFRAC_MSB    5
267#define AR934X_CPU_PLL_CFG_NFRAC_LSB    0
268#define AR934X_CPU_PLL_CFG_NFRAC_MASK   0x0000003f
269
270#define AR934X_CPU_PLL_CFG_NFRAC_GET(x)         \
271        (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >>       \
272        AR934X_CPU_PLL_CFG_NFRAC_LSB)
273
274#define AR934X_CPU_PLL_CFG_NFRAC_SET(x)         \
275        (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) &        \
276        AR934X_CPU_PLL_CFG_NFRAC_MASK)
277
278#define AR934X_DDR_PLL_CFG_REFDIV_MSB   20
279#define AR934X_DDR_PLL_CFG_REFDIV_LSB   16
280#define AR934X_DDR_PLL_CFG_REFDIV_MASK  0x001f0000
281
282#define AR934X_DDR_PLL_CFG_REFDIV_GET(x)                \
283        (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >>      \
284        AR934X_DDR_PLL_CFG_REFDIV_LSB)
285
286#define AR934X_DDR_PLL_CFG_REFDIV_SET(x)                \
287        (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) &       \
288        AR934X_DDR_PLL_CFG_REFDIV_MASK)
289
290#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2
291
292#define AR934X_DDR_PLL_CFG_NINT_MSB     15
293#define AR934X_DDR_PLL_CFG_NINT_LSB     10
294#define AR934X_DDR_PLL_CFG_NINT_MASK    0x0000fc00
295
296#define AR934X_DDR_PLL_CFG_NINT_GET(x)                  \
297        (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >>        \
298        AR934X_DDR_PLL_CFG_NINT_LSB)
299
300#define AR934X_DDR_PLL_CFG_NINT_SET(x)                  \
301        (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) &         \
302        AR934X_DDR_PLL_CFG_NINT_MASK)
303
304#define AR934X_DDR_PLL_CFG_NINT_RESET   20
305
306#define AR934X_DDR_PLL_CFG_NFRAC_MSB    9
307#define AR934X_DDR_PLL_CFG_NFRAC_LSB    0
308#define AR934X_DDR_PLL_CFG_NFRAC_MASK   0x000003ff
309
310#define AR934X_DDR_PLL_CFG_NFRAC_GET(x)         \
311        (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >>       \
312        AR934X_DDR_PLL_CFG_NFRAC_LSB)
313
314#define AR934X_DDR_PLL_CFG_NFRAC_SET(x)         \
315        (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) &        \
316        AR934X_DDR_PLL_CFG_NFRAC_MASK)
317
318#define AR934X_DDR_PLL_CFG_NFRAC_RESET  512
319
320#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB        19
321#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB        15
322#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK       0x000f8000
323
324#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x)             \
325        (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >>   \
326        AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB)
327
328#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x)             \
329        (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) &    \
330        AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
331
332#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET              0
333
334#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB        14
335#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB        10
336#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK       0x00007c00
337
338#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x)             \
339        (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >>   \
340        AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB)
341
342#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x)             \
343        (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) &    \
344        AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
345
346#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET      0
347
348#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB        9
349#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB        5
350#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK       0x000003e0
351
352#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x)             \
353        (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >>   \
354        AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB)
355
356#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x)             \
357        (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) &    \
358        AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
359
360#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET      0
361
362#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB  24
363#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB  24
364#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
365
366#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x)       \
367        (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \
368        AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB)
369
370#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x)       \
371        (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \
372        AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
373
374#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET        1
375
376#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS          BIT(2)
377#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS          BIT(3)
378#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS          BIT(4)
379#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL      BIT(20)
380#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL      BIT(21)
381#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL      BIT(24)
382
383extern void __iomem *ar71xx_pll_base;
384
385static inline void ar71xx_pll_wr(unsigned reg, u32 val)
386{
387        __raw_writel(val, ar71xx_pll_base + reg);
388}
389
390static inline u32 ar71xx_pll_rr(unsigned reg)
391{
392        return __raw_readl(ar71xx_pll_base + reg);
393}
394
395/*
396 * USB_CONFIG block
397 */
398#define USB_CTRL_REG_FLADJ      0x00
399#define USB_CTRL_REG_CONFIG     0x04
400
401extern void __iomem *ar71xx_usb_ctrl_base;
402
403static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
404{
405        __raw_writel(val, ar71xx_usb_ctrl_base + reg);
406}
407
408static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
409{
410        return __raw_readl(ar71xx_usb_ctrl_base + reg);
411}
412
413/*
414 * GPIO block
415 */
416#define GPIO_REG_OE             0x00
417#define GPIO_REG_IN             0x04
418#define GPIO_REG_OUT            0x08
419#define GPIO_REG_SET            0x0c
420#define GPIO_REG_CLEAR          0x10
421#define GPIO_REG_INT_MODE       0x14
422#define GPIO_REG_INT_TYPE       0x18
423#define GPIO_REG_INT_POLARITY   0x1c
424#define GPIO_REG_INT_PENDING    0x20
425#define GPIO_REG_INT_ENABLE     0x24
426#define GPIO_REG_FUNC           0x28
427
428#define AR71XX_GPIO_FUNC_STEREO_EN      BIT(17)
429#define AR71XX_GPIO_FUNC_SLIC_EN        BIT(16)
430#define AR71XX_GPIO_FUNC_SPI_CS2_EN     BIT(13)
431#define AR71XX_GPIO_FUNC_SPI_CS1_EN     BIT(12)
432#define AR71XX_GPIO_FUNC_UART_EN        BIT(8)
433#define AR71XX_GPIO_FUNC_USB_OC_EN      BIT(4)
434#define AR71XX_GPIO_FUNC_USB_CLK_EN     BIT(0)
435
436#define AR71XX_GPIO_COUNT       16
437
438#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN         BIT(19)
439#define AR724X_GPIO_FUNC_SPI_EN                 BIT(18)
440#define AR724X_GPIO_FUNC_SPI_CS_EN2             BIT(14)
441#define AR724X_GPIO_FUNC_SPI_CS_EN1             BIT(13)
442#define AR724X_GPIO_FUNC_CLK_OBS5_EN            BIT(12)
443#define AR724X_GPIO_FUNC_CLK_OBS4_EN            BIT(11)
444#define AR724X_GPIO_FUNC_CLK_OBS3_EN            BIT(10)
445#define AR724X_GPIO_FUNC_CLK_OBS2_EN            BIT(9)
446#define AR724X_GPIO_FUNC_CLK_OBS1_EN            BIT(8)
447#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN     BIT(7)
448#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN     BIT(6)
449#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN     BIT(5)
450#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN     BIT(4)
451#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN     BIT(3)
452#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN        BIT(2)
453#define AR724X_GPIO_FUNC_UART_EN                BIT(1)
454#define AR724X_GPIO_FUNC_JTAG_DISABLE           BIT(0)
455
456#define AR724X_GPIO_COUNT       18
457
458#define AR91XX_GPIO_FUNC_WMAC_LED_EN    BIT(22)
459#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
460#define AR91XX_GPIO_FUNC_I2S_REFCLKEN   BIT(20)
461#define AR91XX_GPIO_FUNC_I2S_MCKEN      BIT(19)
462#define AR91XX_GPIO_FUNC_I2S1_EN        BIT(18)
463#define AR91XX_GPIO_FUNC_I2S0_EN        BIT(17)
464#define AR91XX_GPIO_FUNC_SLIC_EN        BIT(16)
465#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
466#define AR91XX_GPIO_FUNC_UART_EN        BIT(8)
467#define AR91XX_GPIO_FUNC_USB_CLK_EN     BIT(4)
468
469#define AR91XX_GPIO_COUNT       22
470
471#define AR933X_GPIO_COUNT       30
472
473#define AR934X_GPIO_FUNC_SPI_CS_1_EN    BIT(14)
474#define AR934X_GPIO_FUNC_SPI_CS_0_EN    BIT(13)
475
476#define AR934X_GPIO_COUNT               32
477#define AR934X_GPIO_FUNC_DDR_DQOE_EN    BIT(17)
478
479extern void __iomem *ar71xx_gpio_base;
480
481static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
482{
483        __raw_writel(value, ar71xx_gpio_base + reg);
484}
485
486static inline u32 ar71xx_gpio_rr(unsigned reg)
487{
488        return __raw_readl(ar71xx_gpio_base + reg);
489}
490
491void ar71xx_gpio_init(void) __init;
492void ar71xx_gpio_function_enable(u32 mask);
493void ar71xx_gpio_function_disable(u32 mask);
494void ar71xx_gpio_function_setup(u32 set, u32 clear);
495
496/*
497 * DDR_CTRL block
498 */
499#define AR71XX_DDR_REG_PCI_WIN0         0x7c
500#define AR71XX_DDR_REG_PCI_WIN1         0x80
501#define AR71XX_DDR_REG_PCI_WIN2         0x84
502#define AR71XX_DDR_REG_PCI_WIN3         0x88
503#define AR71XX_DDR_REG_PCI_WIN4         0x8c
504#define AR71XX_DDR_REG_PCI_WIN5         0x90
505#define AR71XX_DDR_REG_PCI_WIN6         0x94
506#define AR71XX_DDR_REG_PCI_WIN7         0x98
507#define AR71XX_DDR_REG_FLUSH_GE0        0x9c
508#define AR71XX_DDR_REG_FLUSH_GE1        0xa0
509#define AR71XX_DDR_REG_FLUSH_USB        0xa4
510#define AR71XX_DDR_REG_FLUSH_PCI        0xa8
511
512#define AR724X_DDR_REG_FLUSH_GE0        0x7c
513#define AR724X_DDR_REG_FLUSH_GE1        0x80
514#define AR724X_DDR_REG_FLUSH_USB        0x84
515#define AR724X_DDR_REG_FLUSH_PCIE       0x88
516
517#define AR91XX_DDR_REG_FLUSH_GE0        0x7c
518#define AR91XX_DDR_REG_FLUSH_GE1        0x80
519#define AR91XX_DDR_REG_FLUSH_USB        0x84
520#define AR91XX_DDR_REG_FLUSH_WMAC       0x88
521
522#define AR933X_DDR_REG_FLUSH_GE0        0x7c
523#define AR933X_DDR_REG_FLUSH_GE1        0x80
524#define AR933X_DDR_REG_FLUSH_USB        0x84
525#define AR933X_DDR_REG_FLUSH_WMAC       0x88
526
527#define AR934X_DDR_REG_FLUSH_GE0        0x9c
528#define AR934X_DDR_REG_FLUSH_GE1        0xa0
529#define AR934X_DDR_REG_FLUSH_USB        0xa4
530#define AR934X_DDR_REG_FLUSH_PCIE       0xa8
531
532
533#define PCI_WIN0_OFFS   0x10000000
534#define PCI_WIN1_OFFS   0x11000000
535#define PCI_WIN2_OFFS   0x12000000
536#define PCI_WIN3_OFFS   0x13000000
537#define PCI_WIN4_OFFS   0x14000000
538#define PCI_WIN5_OFFS   0x15000000
539#define PCI_WIN6_OFFS   0x16000000
540#define PCI_WIN7_OFFS   0x07000000
541
542extern void __iomem *ar71xx_ddr_base;
543
544static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
545{
546        __raw_writel(val, ar71xx_ddr_base + reg);
547}
548
549static inline u32 ar71xx_ddr_rr(unsigned reg)
550{
551        return __raw_readl(ar71xx_ddr_base + reg);
552}
553
554void ar71xx_ddr_flush(u32 reg);
555
556/*
557 * PCI block
558 */
559#define AR71XX_PCI_CFG_BASE     (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
560#define AR71XX_PCI_CFG_SIZE     0x100
561
562#define PCI_REG_CRP_AD_CBE      0x00
563#define PCI_REG_CRP_WRDATA      0x04
564#define PCI_REG_CRP_RDDATA      0x08
565#define PCI_REG_CFG_AD          0x0c
566#define PCI_REG_CFG_CBE         0x10
567#define PCI_REG_CFG_WRDATA      0x14
568#define PCI_REG_CFG_RDDATA      0x18
569#define PCI_REG_PCI_ERR         0x1c
570#define PCI_REG_PCI_ERR_ADDR    0x20
571#define PCI_REG_AHB_ERR         0x24
572#define PCI_REG_AHB_ERR_ADDR    0x28
573
574#define PCI_CRP_CMD_WRITE       0x00010000
575#define PCI_CRP_CMD_READ        0x00000000
576#define PCI_CFG_CMD_READ        0x0000000a
577#define PCI_CFG_CMD_WRITE       0x0000000b
578
579#define PCI_IDSEL_ADL_START     17
580
581#define AR724X_PCI_CFG_BASE     (AR71XX_PCI_MEM_BASE + 0x4000000)
582#define AR724X_PCI_CFG_SIZE     0x1000
583
584#define AR724X_PCI_REG_APP              0x00
585#define AR724X_PCI_REG_RESET            0x18
586#define AR724X_PCI_REG_INT_STATUS       0x4c
587#define AR724X_PCI_REG_INT_MASK         0x50
588
589#define AR724X_PCI_APP_LTSSM_ENABLE     BIT(0)
590#define AR724X_PCI_RESET_LINK_UP        BIT(0)
591
592#define AR724X_PCI_INT_DEV0             BIT(14)
593
594/*
595 * RESET block
596 */
597#define AR71XX_RESET_REG_TIMER                  0x00
598#define AR71XX_RESET_REG_TIMER_RELOAD           0x04
599#define AR71XX_RESET_REG_WDOG_CTRL              0x08
600#define AR71XX_RESET_REG_WDOG                   0x0c
601#define AR71XX_RESET_REG_MISC_INT_STATUS        0x10
602#define AR71XX_RESET_REG_MISC_INT_ENABLE        0x14
603#define AR71XX_RESET_REG_PCI_INT_STATUS         0x18
604#define AR71XX_RESET_REG_PCI_INT_ENABLE         0x1c
605#define AR71XX_RESET_REG_GLOBAL_INT_STATUS      0x20
606#define AR71XX_RESET_REG_RESET_MODULE           0x24
607#define AR71XX_RESET_REG_PERFC_CTRL             0x2c
608#define AR71XX_RESET_REG_PERFC0                 0x30
609#define AR71XX_RESET_REG_PERFC1                 0x34
610#define AR71XX_RESET_REG_REV_ID                 0x90
611
612#define AR91XX_RESET_REG_GLOBAL_INT_STATUS      0x18
613#define AR91XX_RESET_REG_RESET_MODULE           0x1c
614#define AR91XX_RESET_REG_PERF_CTRL              0x20
615#define AR91XX_RESET_REG_PERFC0                 0x24
616#define AR91XX_RESET_REG_PERFC1                 0x28
617
618#define AR724X_RESET_REG_RESET_MODULE           0x1c
619
620#define AR933X_RESET_REG_RESET_MODULE           0x1c
621#define AR933X_RESET_REG_BOOTSTRAP              0xac
622#define AR933X_BOOTSTRAP_EEPBUSY                BIT(4)
623#define AR933X_BOOTSTRAP_REF_CLK_40             BIT(0)
624
625#define AR934X_RESET_REG_RESET_MODULE           0x1c
626#define AR934X_RESET_REG_BOOTSTRAP              0xb0
627#define AR934X_BOOTSTRAP_SW_OPTION8             BIT(23)
628#define AR934X_BOOTSTRAP_SW_OPTION7             BIT(22)
629#define AR934X_BOOTSTRAP_SW_OPTION6             BIT(21)
630#define AR934X_BOOTSTRAP_SW_OPTION5             BIT(20)
631#define AR934X_BOOTSTRAP_SW_OPTION4             BIT(19)
632#define AR934X_BOOTSTRAP_SW_OPTION3             BIT(18)
633#define AR934X_BOOTSTRAP_SW_OPTION2             BIT(17)
634#define AR934X_BOOTSTRAP_SW_OPTION1             BIT(16)
635#define AR934X_BOOTSTRAP_USB_MODE_DEVICE        BIT(7)
636#define AR934X_BOOTSTRAP_PCIE_RC                BIT(6)
637#define AR934X_BOOTSTRAP_EJTAG_MODE             BIT(5)
638#define AR934X_BOOTSTRAP_REF_CLK_40             BIT(4)
639#define AR934X_BOOTSTRAP_BOOT_FROM_SPI          BIT(2)
640#define AR934X_BOOTSTRAP_SDRAM_DISABLED         BIT(1)
641#define AR934X_BOOTSTRAP_DDR1                   BIT(0)
642
643#define WDOG_CTRL_LAST_RESET            BIT(31)
644#define WDOG_CTRL_ACTION_MASK           3
645#define WDOG_CTRL_ACTION_NONE           0       /* no action */
646#define WDOG_CTRL_ACTION_GPI            1       /* general purpose interrupt */
647#define WDOG_CTRL_ACTION_NMI            2       /* NMI */
648#define WDOG_CTRL_ACTION_FCR            3       /* full chip reset */
649
650#define MISC_INT_ENET_LINK              BIT(12)
651#define MISC_INT_DDR_PERF               BIT(11)
652#define MISC_INT_TIMER4         BIT(10)
653#define MISC_INT_TIMER3         BIT(9)
654#define MISC_INT_TIMER2         BIT(8)
655#define MISC_INT_DMA                    BIT(7)
656#define MISC_INT_OHCI                   BIT(6)
657#define MISC_INT_PERFC                  BIT(5)
658#define MISC_INT_WDOG                   BIT(4)
659#define MISC_INT_UART                   BIT(3)
660#define MISC_INT_GPIO                   BIT(2)
661#define MISC_INT_ERROR                  BIT(1)
662#define MISC_INT_TIMER                  BIT(0)
663
664#define PCI_INT_CORE                    BIT(4)
665#define PCI_INT_DEV2                    BIT(2)
666#define PCI_INT_DEV1                    BIT(1)
667#define PCI_INT_DEV0                    BIT(0)
668
669#define RESET_MODULE_EXTERNAL           BIT(28)
670#define RESET_MODULE_FULL_CHIP          BIT(24)
671#define RESET_MODULE_AMBA2WMAC          BIT(22)
672#define RESET_MODULE_CPU_NMI            BIT(21)
673#define RESET_MODULE_CPU_COLD           BIT(20)
674#define RESET_MODULE_DMA                BIT(19)
675#define RESET_MODULE_SLIC               BIT(18)
676#define RESET_MODULE_STEREO             BIT(17)
677#define RESET_MODULE_DDR                BIT(16)
678#define RESET_MODULE_GE1_MAC            BIT(13)
679#define RESET_MODULE_GE1_PHY            BIT(12)
680#define RESET_MODULE_USBSUS_OVERRIDE    BIT(10)
681#define RESET_MODULE_GE0_MAC            BIT(9)
682#define RESET_MODULE_GE0_PHY            BIT(8)
683#define RESET_MODULE_USB_OHCI_DLL       BIT(6)
684#define RESET_MODULE_USB_HOST           BIT(5)
685#define RESET_MODULE_USB_PHY            BIT(4)
686#define RESET_MODULE_USB_OHCI_DLL_7240  BIT(3)
687#define RESET_MODULE_PCI_BUS            BIT(1)
688#define RESET_MODULE_PCI_CORE           BIT(0)
689
690#define AR724X_RESET_GE1_MDIO           BIT(23)
691#define AR724X_RESET_GE0_MDIO           BIT(22)
692#define AR724X_RESET_PCIE_PHY_SERIAL    BIT(10)
693#define AR724X_RESET_PCIE_PHY           BIT(7)
694#define AR724X_RESET_PCIE               BIT(6)
695#define AR724X_RESET_USB_HOST           BIT(5)
696#define AR724X_RESET_USB_PHY            BIT(4)
697#define AR724X_RESET_USBSUS_OVERRIDE    BIT(3)
698
699#define AR933X_RESET_WMAC               BIT(11)
700#define AR933X_RESET_GE1_MDIO           BIT(23)
701#define AR933X_RESET_GE0_MDIO           BIT(22)
702#define AR933X_RESET_GE1_MAC            BIT(13)
703#define AR933X_RESET_GE0_MAC            BIT(9)
704#define AR933X_RESET_USB_HOST           BIT(5)
705#define AR933X_RESET_USB_PHY            BIT(4)
706#define AR933X_RESET_USBSUS_OVERRIDE    BIT(3)
707
708#define AR934X_RESET_HOST               BIT(31)
709#define AR934X_RESET_SLIC               BIT(30)
710#define AR934X_RESET_HDMA               BIT(29)
711#define AR934X_RESET_EXTERNAL           BIT(28)
712#define AR934X_RESET_RTC                BIT(27)
713#define AR934X_RESET_PCIE_EP_INT        BIT(26)
714#define AR934X_RESET_CHKSUM_ACC         BIT(25)
715#define AR934X_RESET_FULL_CHIP          BIT(24)
716#define AR934X_RESET_GE1_MDIO           BIT(23)
717#define AR934X_RESET_GE0_MDIO           BIT(22)
718#define AR934X_RESET_CPU_NMI            BIT(21)
719#define AR934X_RESET_CPU_COLD           BIT(20)
720#define AR934X_RESET_HOST_RESET_INT     BIT(19)
721#define AR934X_RESET_PCIE_EP            BIT(18)
722#define AR934X_RESET_UART1              BIT(17)
723#define AR934X_RESET_DDR                BIT(16)
724#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
725#define AR934X_RESET_NANDF              BIT(14)
726#define AR934X_RESET_GE1_MAC            BIT(13)
727#define AR934X_RESET_ETH_SWITCH_ANALOG  BIT(12)
728#define AR934X_RESET_USB_PHY_ANALOG     BIT(11)
729#define AR934X_RESET_HOST_DMA_INT       BIT(10)
730#define AR934X_RESET_GE0_MAC            BIT(9)
731#define AR934X_RESET_ETH_SIWTCH         BIT(8)
732#define AR934X_RESET_PCIE_PHY           BIT(7)
733#define AR934X_RESET_PCIE               BIT(6)
734#define AR934X_RESET_USB_HOST           BIT(5)
735#define AR934X_RESET_USB_PHY            BIT(4)
736#define AR934X_RESET_USBSUS_OVERRIDE    BIT(3)
737#define AR934X_RESET_LUT                BIT(2)
738#define AR934X_RESET_MBOX               BIT(1)
739#define AR934X_RESET_I2S                BIT(0)
740
741#define REV_ID_MAJOR_MASK       0xfff0
742#define REV_ID_MAJOR_AR71XX     0x00a0
743#define REV_ID_MAJOR_AR913X     0x00b0
744#define REV_ID_MAJOR_AR7240     0x00c0
745#define REV_ID_MAJOR_AR7241     0x0100
746#define REV_ID_MAJOR_AR7242     0x1100
747#define REV_ID_MAJOR_AR9330     0x0110
748#define REV_ID_MAJOR_AR9331     0x1110
749#define REV_ID_MAJOR_AR9341     0x0120
750#define REV_ID_MAJOR_AR9342     0x1120
751#define REV_ID_MAJOR_AR9344     0x2120
752
753#define AR71XX_REV_ID_MINOR_MASK        0x3
754#define AR71XX_REV_ID_MINOR_AR7130      0x0
755#define AR71XX_REV_ID_MINOR_AR7141      0x1
756#define AR71XX_REV_ID_MINOR_AR7161      0x2
757#define AR71XX_REV_ID_REVISION_MASK     0x3
758#define AR71XX_REV_ID_REVISION_SHIFT    2
759
760#define AR91XX_REV_ID_MINOR_MASK        0x3
761#define AR91XX_REV_ID_MINOR_AR9130      0x0
762#define AR91XX_REV_ID_MINOR_AR9132      0x1
763#define AR91XX_REV_ID_REVISION_MASK     0x3
764#define AR91XX_REV_ID_REVISION_SHIFT    2
765
766#define AR724X_REV_ID_REVISION_MASK     0x3
767
768#define AR933X_REV_ID_REVISION_MASK     0xf
769
770#define AR934X_REV_ID_REVISION_MASK     0xf
771
772extern void __iomem *ar71xx_reset_base;
773
774static inline void ar71xx_reset_wr(unsigned reg, u32 val)
775{
776        __raw_writel(val, ar71xx_reset_base + reg);
777}
778
779static inline u32 ar71xx_reset_rr(unsigned reg)
780{
781        return __raw_readl(ar71xx_reset_base + reg);
782}
783
784void ar71xx_device_stop(u32 mask);
785void ar71xx_device_start(u32 mask);
786void ar71xx_device_reset_rmw(u32 clear, u32 set);
787int ar71xx_device_stopped(u32 mask);
788
789/*
790 * SPI block
791 */
792#define SPI_REG_FS              0x00    /* Function Select */
793#define SPI_REG_CTRL            0x04    /* SPI Control */
794#define SPI_REG_IOC             0x08    /* SPI I/O Control */
795#define SPI_REG_RDS             0x0c    /* Read Data Shift */
796
797#define SPI_FS_GPIO             BIT(0)  /* Enable GPIO mode */
798
799#define SPI_CTRL_RD             BIT(6)  /* Remap Disable */
800#define SPI_CTRL_DIV_MASK       0x3f
801
802#define SPI_IOC_DO              BIT(0)  /* Data Out pin */
803#define SPI_IOC_CLK             BIT(8)  /* CLK pin */
804#define SPI_IOC_CS(n)           BIT(16 + (n))
805#define SPI_IOC_CS0             SPI_IOC_CS(0)
806#define SPI_IOC_CS1             SPI_IOC_CS(1)
807#define SPI_IOC_CS2             SPI_IOC_CS(2)
808#define SPI_IOC_CS_ALL          (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
809
810void ar71xx_flash_acquire(void);
811void ar71xx_flash_release(void);
812
813/*
814 * MII_CTRL block
815 */
816#define MII_REG_MII0_CTRL       0x00
817#define MII_REG_MII1_CTRL       0x04
818
819#define MII_CTRL_IF_MASK        3
820
821#define MII0_CTRL_IF_GMII       0
822#define MII0_CTRL_IF_MII        1
823#define MII0_CTRL_IF_RGMII      2
824#define MII0_CTRL_IF_RMII       3
825
826#define MII1_CTRL_IF_RGMII      0
827#define MII1_CTRL_IF_RMII       1
828
829/*
830 * AR933X GMAC
831 */
832#define AR933X_GMAC_REG_ETH_CFG         0x00
833
834#define AR933X_ETH_CFG_RGMII_GE0        BIT(0)
835#define AR933X_ETH_CFG_MII_GE0          BIT(1)
836#define AR933X_ETH_CFG_GMII_GE0         BIT(2)
837#define AR933X_ETH_CFG_MII_GE0_MASTER   BIT(3)
838#define AR933X_ETH_CFG_MII_GE0_SLAVE    BIT(4)
839#define AR933X_ETH_CFG_MII_GE0_ERR_EN   BIT(5)
840#define AR933X_ETH_CFG_SW_PHY_SWAP      BIT(7)
841#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
842#define AR933X_ETH_CFG_RMII_GE0         BIT(9)
843#define AR933X_ETH_CFG_RMII_GE0_SPD_10  0
844#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
845
846#endif /* __ASSEMBLER__ */
847
848#endif /* __ASM_MACH_AR71XX_H */
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