source: trunk/target/linux/ar71xx/patches-2.6.34/902-mips_clocksource_init_war.patch @ 20141

Last change on this file since 20141 was 20141, checked in by acoul, 7 years ago

ar71xx: add 2.6.34 preliminary support (patches)

File size: 1.6 KB
  • arch/mips/kernel/cevt-r4k.c

    a b  
    1616#include <asm/cevt-r4k.h> 
    1717 
    1818/* 
     19 * Compare interrupt can be routed and latched outside the core, 
     20 * so a single execution hazard barrier may not be enough to give 
     21 * it time to clear as seen in the Cause register.  4 time the 
     22 * pipeline depth seems reasonably conservative, and empirically 
     23 * works better in configurations with high CPU/bus clock ratios. 
     24 */ 
     25 
     26#define compare_change_hazard() \ 
     27        do { \ 
     28                irq_disable_hazard(); \ 
     29                irq_disable_hazard(); \ 
     30                irq_disable_hazard(); \ 
     31                irq_disable_hazard(); \ 
     32        } while (0) 
     33 
     34/* 
    1935 * The SMTC Kernel for the 34K, 1004K, et. al. replaces several 
    2036 * of these routines with SMTC-specific variants. 
    2137 */ 
    static int mips_next_event(unsigned long 
    3147        cnt = read_c0_count(); 
    3248        cnt += delta; 
    3349        write_c0_compare(cnt); 
     50        compare_change_hazard(); 
    3451        res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; 
    3552        return res; 
    3653} 
    static int c0_compare_int_pending(void) 
    100117        return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); 
    101118} 
    102119 
    103 /* 
    104  * Compare interrupt can be routed and latched outside the core, 
    105  * so a single execution hazard barrier may not be enough to give 
    106  * it time to clear as seen in the Cause register.  4 time the 
    107  * pipeline depth seems reasonably conservative, and empirically 
    108  * works better in configurations with high CPU/bus clock ratios. 
    109  */ 
    110  
    111 #define compare_change_hazard() \ 
    112         do { \ 
    113                 irq_disable_hazard(); \ 
    114                 irq_disable_hazard(); \ 
    115                 irq_disable_hazard(); \ 
    116                 irq_disable_hazard(); \ 
    117         } while (0) 
    118  
    119120int c0_compare_int_usable(void) 
    120121{ 
    121122        unsigned int delta; 
Note: See TracBrowser for help on using the repository browser.