source: trunk/target/linux/ar71xx/patches-3.3/126-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch @ 30410

Last change on this file since 30410 was 30410, checked in by juhosg, 5 years ago

ar71xx: add preliminary support for 3.3

File size: 4.4 KB
  • arch/mips/ath79/irq.c

    From e69d89040d4884ea4069352338f555694e65fe70 Mon Sep 17 00:00:00 2001
    From: Gabor Juhos <juhosg@openwrt.org>
    Date: Fri, 9 Dec 2011 21:30:03 +0100
    Subject: [PATCH 26/35] MIPS: ath79: rework IP2/IP3 interrupt handling
    
    The current implementation assumes that flushing the
    DDR writeback buffer is required for IP2/IP3 interrupts,
    however this is not true for all SoCs.
    
    Use SoC specific IP2/IP3 handlers instead of flushing
    the buffers in the dispatcher code.
    
    Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
    Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
    ---
     arch/mips/ath79/irq.c |   92 ++++++++++++++++++++++++++++++++++++++-----------
     1 files changed, 72 insertions(+), 20 deletions(-)
    
    a b  
    11/* 
    22 *  Atheros AR71xx/AR724x/AR913x specific interrupt handling 
    33 * 
    4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 
     4 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 
    55 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 
    66 * 
    77 *  Parts of this file are based on Atheros' 2.6.15 BSP 
     
    2323#include <asm/mach-ath79/ar71xx_regs.h> 
    2424#include "common.h" 
    2525 
    26 static unsigned int ath79_ip2_flush_reg; 
    27 static unsigned int ath79_ip3_flush_reg; 
     26static void (*ath79_ip2_handler)(void); 
     27static void (*ath79_ip3_handler)(void); 
    2828 
    2929static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) 
    3030{ 
    asmlinkage void plat_irq_dispatch(void) 
    152152        if (pending & STATUSF_IP7) 
    153153                do_IRQ(ATH79_CPU_IRQ_TIMER); 
    154154 
    155         else if (pending & STATUSF_IP2) { 
    156                 ath79_ddr_wb_flush(ath79_ip2_flush_reg); 
    157                 do_IRQ(ATH79_CPU_IRQ_IP2); 
    158         } 
     155        else if (pending & STATUSF_IP2) 
     156                ath79_ip2_handler(); 
    159157 
    160158        else if (pending & STATUSF_IP4) 
    161159                do_IRQ(ATH79_CPU_IRQ_GE0); 
    asmlinkage void plat_irq_dispatch(void) 
    163161        else if (pending & STATUSF_IP5) 
    164162                do_IRQ(ATH79_CPU_IRQ_GE1); 
    165163 
    166         else if (pending & STATUSF_IP3) { 
    167                 ath79_ddr_wb_flush(ath79_ip3_flush_reg); 
    168                 do_IRQ(ATH79_CPU_IRQ_USB); 
    169         } 
     164        else if (pending & STATUSF_IP3) 
     165                ath79_ip3_handler(); 
    170166 
    171167        else if (pending & STATUSF_IP6) 
    172168                do_IRQ(ATH79_CPU_IRQ_MISC); 
    asmlinkage void plat_irq_dispatch(void) 
    175171                spurious_interrupt(); 
    176172} 
    177173 
     174/* 
     175 * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for 
     176 * these devices typically allocate coherent DMA memory, however the 
     177 * DMA controller may still have some unsynchronized data in the FIFO. 
     178 * Issue a flush in the handlers to ensure that the driver sees 
     179 * the update. 
     180 */ 
     181static void ar71xx_ip2_handler(void) 
     182{ 
     183        ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); 
     184        do_IRQ(ATH79_CPU_IRQ_IP2); 
     185} 
     186 
     187static void ar724x_ip2_handler(void) 
     188{ 
     189        ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); 
     190        do_IRQ(ATH79_CPU_IRQ_IP2); 
     191} 
     192 
     193static void ar913x_ip2_handler(void) 
     194{ 
     195        ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); 
     196        do_IRQ(ATH79_CPU_IRQ_IP2); 
     197} 
     198 
     199static void ar933x_ip2_handler(void) 
     200{ 
     201        ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); 
     202        do_IRQ(ATH79_CPU_IRQ_IP2); 
     203} 
     204 
     205static void ar71xx_ip3_handler(void) 
     206{ 
     207        ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); 
     208        do_IRQ(ATH79_CPU_IRQ_USB); 
     209} 
     210 
     211static void ar724x_ip3_handler(void) 
     212{ 
     213        ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); 
     214        do_IRQ(ATH79_CPU_IRQ_USB); 
     215} 
     216 
     217static void ar913x_ip3_handler(void) 
     218{ 
     219        ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); 
     220        do_IRQ(ATH79_CPU_IRQ_USB); 
     221} 
     222 
     223static void ar933x_ip3_handler(void) 
     224{ 
     225        ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); 
     226        do_IRQ(ATH79_CPU_IRQ_USB); 
     227} 
     228 
    178229void __init arch_init_irq(void) 
    179230{ 
    180231        if (soc_is_ar71xx()) { 
    181                 ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; 
    182                 ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB; 
     232                ath79_ip2_handler = ar71xx_ip2_handler; 
     233                ath79_ip3_handler = ar71xx_ip3_handler; 
    183234        } else if (soc_is_ar724x()) { 
    184                 ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; 
    185                 ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB; 
     235                ath79_ip2_handler = ar724x_ip2_handler; 
     236                ath79_ip3_handler = ar724x_ip3_handler; 
    186237        } else if (soc_is_ar913x()) { 
    187                 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; 
    188                 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; 
     238                ath79_ip2_handler = ar913x_ip2_handler; 
     239                ath79_ip3_handler = ar913x_ip3_handler; 
    189240        } else if (soc_is_ar933x()) { 
    190                 ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC; 
    191                 ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB; 
    192         } else 
     241                ath79_ip2_handler = ar933x_ip2_handler; 
     242                ath79_ip3_handler = ar933x_ip3_handler; 
     243        } else { 
    193244                BUG(); 
     245        } 
    194246 
    195247        cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; 
    196248        mips_cpu_irq_init(); 
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