source: trunk/target/linux/brcm47xx/patches-3.0/0007-bcma-get-CPU-clock.patch @ 27301

Last change on this file since 27301 was 27301, checked in by hauke, 5 years ago

brcm47xx: add initial support for devices with bcma bus.

Ethernet and wifi are not working and this is highly experimental.

File size: 6.3 KB
  • drivers/bcma/bcma_private.h

    From 257d5fe12600f08df764cac0abc17bef7b6fae9b Mon Sep 17 00:00:00 2001
    From: Hauke Mehrtens <hauke@hauke-m.de>
    Date: Sun, 19 Jun 2011 17:51:30 +0200
    Subject: [PATCH 07/14] bcma: get CPU clock
    
    Add method to return the clock of the CPU. This is needed by the arch
    code to calculate the mips_hpt_frequency.
    
    Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
    ---
     drivers/bcma/bcma_private.h                 |    3 +
     drivers/bcma/driver_chipcommon_pmu.c        |   87 +++++++++++++++++++++++++++
     drivers/bcma/driver_mips.c                  |   12 ++++
     include/linux/bcma/bcma_driver_chipcommon.h |   35 +++++++++++
     include/linux/bcma/bcma_driver_mips.h       |    1 +
     5 files changed, 138 insertions(+), 0 deletions(-)
    
    a b void bcma_init_bus(struct bcma_bus *bus) 
    2929/* sprom.c */ 
    3030int bcma_sprom_get(struct bcma_bus *bus); 
    3131 
     32/* driver_chipcommon_pmu.c */ 
     33extern u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc); 
     34 
    3235/* driver_chipcommon.c */ 
    3336#ifdef CONFIG_BCMA_DRIVER_MIPS 
    3437extern int bcma_chipco_serial_init(struct bcma_drv_cc *cc, 
  • drivers/bcma/driver_chipcommon_pmu.c

    a b  
    1111#include "bcma_private.h" 
    1212#include <linux/bcma/bcma.h> 
    1313 
     14static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) 
     15{ 
     16        bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 
     17        bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); 
     18        return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); 
     19} 
     20 
    1421static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, 
    1522                                        u32 offset, u32 mask, u32 set) 
    1623{ 
    void bcma_pmu_init(struct bcma_drv_cc *c 
    136143        bcma_pmu_swreg_init(cc); 
    137144        bcma_pmu_workarounds(cc); 
    138145} 
     146 
     147static u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc) 
     148{ 
     149        struct bcma_bus *bus = cc->core->bus; 
     150 
     151        switch (bus->chipinfo.id) { 
     152        case 0x4716: 
     153        case 0x4748: 
     154        case 47162: 
     155                /* always 20Mhz */ 
     156                return 20000 * 1000; 
     157        default: 
     158                pr_warn("No ALP clock specified for %04X device, " 
     159                        "pmu rev. %d, using default %d Hz\n", 
     160                        bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); 
     161        } 
     162        return BCMA_CC_PMU_ALP_CLOCK; 
     163} 
     164 
     165/* Find the output of the "m" pll divider given pll controls that start with 
     166 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. 
     167 */ 
     168static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) 
     169{ 
     170        u32 tmp, div, ndiv, p1, p2, fc; 
     171 
     172        BUG_ON(!m || m > 4); 
     173 
     174        BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); 
     175 
     176        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); 
     177        p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT; 
     178        p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT; 
     179 
     180        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); 
     181        div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) & 
     182                BCMA_CC_PPL_MDIV_MASK; 
     183 
     184        tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF); 
     185        ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; 
     186 
     187        /* Do calculation in Mhz */ 
     188        fc = bcma_pmu_alp_clock(cc) / 1000000; 
     189        fc = (p1 * ndiv * fc) / p2; 
     190 
     191        /* Return clock in Hertz */ 
     192        return (fc / div) * 1000000; 
     193} 
     194 
     195/* query bus clock frequency for PMU-enabled chipcommon */ 
     196u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc) 
     197{ 
     198        struct bcma_bus *bus = cc->core->bus; 
     199 
     200        switch (bus->chipinfo.id) { 
     201        case 0x4716: 
     202        case 0x4748: 
     203        case 47162: 
     204                return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, 
     205                                      BCMA_CC_PMU5_MAINPLL_SSB); 
     206        default: 
     207                pr_warn("No backplane clock specified for %04X device, " 
     208                        "pmu rev. %d, using default %d Hz\n", 
     209                        bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK); 
     210        } 
     211        return BCMA_CC_PMU_HT_CLOCK; 
     212} 
     213 
     214/* query cpu clock frequency for PMU-enabled chipcommon */ 
     215u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc) 
     216{ 
     217        struct bcma_bus *bus = cc->core->bus; 
     218 
     219        if ((cc->pmu.rev == 5 || cc->pmu.rev == 6 || cc->pmu.rev == 7) && 
     220            (bus->chipinfo.id != 0x4319)) 
     221                return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, 
     222                                      BCMA_CC_PMU5_MAINPLL_CPU); 
     223 
     224        return bcma_pmu_get_clockcontrol(cc); 
     225} 
  • drivers/bcma/driver_mips.c

    a b static void bcma_core_mips_dump_irq(stru 
    157157        } 
    158158} 
    159159 
     160u32 bcma_cpu_clock(struct bcma_drv_mips *mcore) 
     161{ 
     162        struct bcma_bus *bus = mcore->core->bus; 
     163 
     164        if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) 
     165                return bcma_pmu_get_clockcpu(&bus->drv_cc); 
     166 
     167        pr_err("No PMU available, need this to get the cpu clock\n"); 
     168        return 0; 
     169} 
     170EXPORT_SYMBOL(bcma_cpu_clock); 
     171 
    160172static void bcma_core_mips_serial_init(struct bcma_drv_mips *mcore) 
    161173{ 
    162174        struct bcma_bus *bus = mcore->core->bus; 
  • include/linux/bcma/bcma_driver_chipcommon.h

    a b  
    246246#define BCMA_CC_PLLCTL_DATA             0x0664 
    247247#define BCMA_CC_SPROM                   0x0830 /* SPROM beginning */ 
    248248 
     249/* Divider allocation in 4716/47162/5356 */ 
     250#define BCMA_CC_PMU5_MAINPLL_CPU        1 
     251#define BCMA_CC_PMU5_MAINPLL_MEM        2 
     252#define BCMA_CC_PMU5_MAINPLL_SSB        3 
     253 
     254/* PLL usage in 4716/47162 */ 
     255#define BCMA_CC_PMU4716_MAINPLL_PLL0    12 
     256 
     257/* ALP clock on pre-PMU chips */ 
     258#define BCMA_CC_PMU_ALP_CLOCK           20000000 
     259/* HT clock for systems with PMU-enabled chipcommon */ 
     260#define BCMA_CC_PMU_HT_CLOCK            80000000 
     261 
     262/* PMU rev 5 (& 6) */ 
     263#define BCMA_CC_PPL_P1P2_OFF            0 
     264#define BCMA_CC_PPL_P1_MASK             0x0f000000 
     265#define BCMA_CC_PPL_P1_SHIFT            24 
     266#define BCMA_CC_PPL_P2_MASK             0x00f00000 
     267#define BCMA_CC_PPL_P2_SHIFT            20 
     268#define BCMA_CC_PPL_M14_OFF             1 
     269#define BCMA_CC_PPL_MDIV_MASK           0x000000ff 
     270#define BCMA_CC_PPL_MDIV_WIDTH          8 
     271#define BCMA_CC_PPL_NM5_OFF             2 
     272#define BCMA_CC_PPL_NDIV_MASK           0xfff00000 
     273#define BCMA_CC_PPL_NDIV_SHIFT          20 
     274#define BCMA_CC_PPL_FMAB_OFF            3 
     275#define BCMA_CC_PPL_MRAT_MASK           0xf0000000 
     276#define BCMA_CC_PPL_MRAT_SHIFT          28 
     277#define BCMA_CC_PPL_ABRAT_MASK          0x08000000 
     278#define BCMA_CC_PPL_ABRAT_SHIFT         27 
     279#define BCMA_CC_PPL_FDIV_MASK           0x07ffffff 
     280#define BCMA_CC_PPL_PLLCTL_OFF          4 
     281#define BCMA_CC_PPL_PCHI_OFF            5 
     282#define BCMA_CC_PPL_PCHI_MASK           0x0000003f 
     283 
    249284/* Data for the PMU, if available. 
    250285 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) 
    251286 */ 
  • include/linux/bcma/bcma_driver_mips.h

    a b struct bcma_drv_mips { 
    5454}; 
    5555 
    5656extern void bcma_core_mips_init(struct bcma_drv_mips *mcore); 
     57extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore); 
    5758 
    5859extern unsigned int bcma_core_mips_irq(struct bcma_device *dev); 
    5960 
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