source: trunk/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h @ 18259

Last change on this file since 18259 was 18259, checked in by blogic, 6 years ago

[ifxmips] adds dsl support, thank you infineon/lantiq

File size: 3.0 KB
Line 
1/*
2 *   This program is free software; you can redistribute it and/or modify
3 *   it under the terms of the GNU General Public License as published by
4 *   the Free Software Foundation; either version 2 of the License, or
5 *   (at your option) any later version.
6 *
7 *   This program is distributed in the hope that it will be useful,
8 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
9 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10 *   GNU General Public License for more details.
11 *
12 *   You should have received a copy of the GNU General Public License
13 *   along with this program; if not, write to the Free Software
14 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 *   Copyright (C) 2005 infineon
17 *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 */
19#ifndef _IFXMIPS_IRQ__
20#define _IFXMIPS_IRQ__
21
22#define INT_NUM_IRQ0                    8
23#define INT_NUM_IM0_IRL0                (INT_NUM_IRQ0 + 0)
24#define INT_NUM_IM1_IRL0                (INT_NUM_IRQ0 + 32)
25#define INT_NUM_IM2_IRL0                (INT_NUM_IRQ0 + 64)
26#define INT_NUM_IM3_IRL0                (INT_NUM_IRQ0 + 96)
27#define INT_NUM_IM4_IRL0                (INT_NUM_IRQ0 + 128)
28#define INT_NUM_IM_OFFSET               (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
29
30#define IFXMIPSASC_TIR(x)               (INT_NUM_IM3_IRL0 + (x * 7))
31#define IFXMIPSASC_RIR(x)               (INT_NUM_IM3_IRL0 + (x * 7) + 2)
32#define IFXMIPSASC_EIR(x)               (INT_NUM_IM3_IRL0 + (x * 7) + 3)
33
34#define IFXMIPS_SSC_TIR                 (INT_NUM_IM0_IRL0 + 15)
35#define IFXMIPS_SSC_RIR                 (INT_NUM_IM0_IRL0 + 14)
36#define IFXMIPS_SSC_EIR                 (INT_NUM_IM0_IRL0 + 16)
37
38#define IFXMIPS_MEI_DYING_GASP_INT      (INT_NUM_IM1_IRL0 + 21)
39#define IFXMIPS_MEI_INT                 (INT_NUM_IM1_IRL0 + 23)
40
41#define IFXMIPS_TIMER6_INT              (INT_NUM_IM1_IRL0 + 23)
42#define IFXMIPS_USB_OC_INT              (INT_NUM_IM4_IRL0 + 23)
43
44#define MIPS_CPU_TIMER_IRQ              7
45
46#define IFXMIPS_DMA_CH0_INT             (INT_NUM_IM2_IRL0)
47#define IFXMIPS_DMA_CH1_INT             (INT_NUM_IM2_IRL0 + 1)
48#define IFXMIPS_DMA_CH2_INT             (INT_NUM_IM2_IRL0 + 2)
49#define IFXMIPS_DMA_CH3_INT             (INT_NUM_IM2_IRL0 + 3)
50#define IFXMIPS_DMA_CH4_INT             (INT_NUM_IM2_IRL0 + 4)
51#define IFXMIPS_DMA_CH5_INT             (INT_NUM_IM2_IRL0 + 5)
52#define IFXMIPS_DMA_CH6_INT             (INT_NUM_IM2_IRL0 + 6)
53#define IFXMIPS_DMA_CH7_INT             (INT_NUM_IM2_IRL0 + 7)
54#define IFXMIPS_DMA_CH8_INT             (INT_NUM_IM2_IRL0 + 8)
55#define IFXMIPS_DMA_CH9_INT             (INT_NUM_IM2_IRL0 + 9)
56#define IFXMIPS_DMA_CH10_INT            (INT_NUM_IM2_IRL0 + 10)
57#define IFXMIPS_DMA_CH11_INT            (INT_NUM_IM2_IRL0 + 11)
58#define IFXMIPS_DMA_CH12_INT            (INT_NUM_IM2_IRL0 + 25)
59#define IFXMIPS_DMA_CH13_INT            (INT_NUM_IM2_IRL0 + 26)
60#define IFXMIPS_DMA_CH14_INT            (INT_NUM_IM2_IRL0 + 27)
61#define IFXMIPS_DMA_CH15_INT            (INT_NUM_IM2_IRL0 + 28)
62#define IFXMIPS_DMA_CH16_INT            (INT_NUM_IM2_IRL0 + 29)
63#define IFXMIPS_DMA_CH17_INT            (INT_NUM_IM2_IRL0 + 30)
64#define IFXMIPS_DMA_CH18_INT            (INT_NUM_IM2_IRL0 + 16)
65#define IFXMIPS_DMA_CH19_INT            (INT_NUM_IM2_IRL0 + 21)
66
67#define IFXMIPS_PPE_MBOX_INT            (INT_NUM_IM2_IRL0 + 24)
68
69#define IFXMIPS_USB_INT                 (INT_NUM_IM4_IRL0 + 22)
70#define IFXMIPS_USB_OC_INT              (INT_NUM_IM4_IRL0 + 23)
71
72
73extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
74
75#endif
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