source: trunk/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch @ 17817

Last change on this file since 17817 was 17817, checked in by blogic, 7 years ago

bump ifxmips to .30

File size: 1.1 KB
  • arch/mips/kernel/cevt-r4k.c

    old new  
    2121 
    2222#ifndef CONFIG_MIPS_MT_SMTC 
    2323 
     24/* 
     25 * Compare interrupt can be routed and latched outside the core, 
     26 * so a single execution hazard barrier may not be enough to give 
     27 * it time to clear as seen in the Cause register.  4 time the 
     28 * pipeline depth seems reasonably conservative, and empirically 
     29 * works better in configurations with high CPU/bus clock ratios. 
     30 */ 
     31 
     32#define compare_change_hazard() \ 
     33        do { \ 
     34                irq_disable_hazard(); \ 
     35                irq_disable_hazard(); \ 
     36                irq_disable_hazard(); \ 
     37                irq_disable_hazard(); \ 
     38        } while (0) 
     39 
    2440static int mips_next_event(unsigned long delta, 
    2541                           struct clock_event_device *evt) 
    2642{ 
     
    3046        cnt = read_c0_count(); 
    3147        cnt += delta; 
    3248        write_c0_compare(cnt); 
     49        compare_change_hazard(); 
    3350        res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; 
    3451        return res; 
    3552} 
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