source: trunk/target/linux/lantiq/patches-3.0/0016-MIPS-lantiq-adds-xway-nand-driver.patch @ 28405

Last change on this file since 28405 was 28405, checked in by blogic, 5 years ago

[lantiq]

  • update patches to 3.0
  • add basic vr9 support
  • backport 3.1 fixes
  • backport 3.2 queue (falcon)
File size: 8.7 KB
  • arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h

    From e2d5b4ba92289cb0fcc9db741d159ef5eb852d9f Mon Sep 17 00:00:00 2001
    From: John Crispin <blogic@openwrt.org>
    Date: Sat, 27 Aug 2011 20:08:14 +0200
    Subject: [PATCH 16/24] MIPS: lantiq: adds xway nand driver
    
    This patch adds a nand driver for XWAY SoCs. The patch makes use of the
    plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the
    endianess swap problem on read. To workaround this problem we make the
    read_byte() callback available via the plat_nand driver causing the nand
    layer to do byte reads.
    
    Signed-off-by: John Crispin <blogic@openwrt.org>
    
    TODO : memory ranges
           cs lines
           plat dev
           ebu2 and not ebu1 ?
    ---
     .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    2 +
     arch/mips/lantiq/xway/Makefile                     |    2 +-
     arch/mips/lantiq/xway/nand.c                       |  185 ++++++++++++++++++++
     drivers/mtd/nand/plat_nand.c                       |    1 +
     include/linux/mtd/nand.h                           |    1 +
     5 files changed, 190 insertions(+), 1 deletions(-)
     create mode 100644 arch/mips/lantiq/xway/nand.c
    
    diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
    index 86ed0d2..729dfa2 100644
    a b  
    140140/* register access macros for EBU and CGU */ 
    141141#define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y)) 
    142142#define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x)) 
     143#define ltq_ebu_w32_mask(x, y, z) \ 
     144        ltq_w32_mask(x, y, ltq_ebu_membase + (z)) 
    143145#define ltq_cgu_w32(x, y)       ltq_w32((x), ltq_cgu_membase + (y)) 
    144146#define ltq_cgu_r32(x)          ltq_r32(ltq_cgu_membase + (x)) 
    145147 
  • arch/mips/lantiq/xway/Makefile

    diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
    index 6678402..ac7cc34 100644
    a b  
    1 obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o 
     1obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o 
    22 
    33obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o 
    44obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o 
  • new file arch/mips/lantiq/xway/nand.c

    diff --git a/arch/mips/lantiq/xway/nand.c b/arch/mips/lantiq/xway/nand.c
    new file mode 100644
    index 0000000..ba2443c
    - +  
     1/* 
     2 *  This program is free software; you can redistribute it and/or modify it 
     3 *  under the terms of the GNU General Public License version 2 as published 
     4 *  by the Free Software Foundation. 
     5 * 
     6 *  Copyright (C) 2010 John Crispin <blogic@openwrt.org> 
     7 */ 
     8 
     9#include <linux/mtd/physmap.h> 
     10#include <linux/mtd/nand.h> 
     11#include <linux/platform_device.h> 
     12 
     13#include <lantiq_soc.h> 
     14#include <lantiq_irq.h> 
     15#include <lantiq_platform.h> 
     16 
     17#include "devices.h" 
     18 
     19/* nand registers */ 
     20#define LTQ_EBU_NAND_WAIT       0xB4 
     21#define LTQ_EBU_NAND_ECC0       0xB8 
     22#define LTQ_EBU_NAND_ECC_AC     0xBC 
     23#define LTQ_EBU_NAND_CON        0xB0 
     24#define LTQ_EBU_ADDSEL1         0x24 
     25 
     26/* gpio definitions */ 
     27#define PIN_ALE    13 
     28#define PIN_CLE    24 
     29#define PIN_CS1    23 
     30#define PIN_RDY    48  /* NFLASH_READY */ 
     31#define PIN_RD     49  /* NFLASH_READ_N */ 
     32 
     33#define NAND_CMD_ALE            (1 << 2) 
     34#define NAND_CMD_CLE            (1 << 3) 
     35#define NAND_CMD_CS             (1 << 4) 
     36#define NAND_WRITE_CMD_RESET    0xff 
     37#define NAND_WRITE_CMD          (NAND_CMD_CS | NAND_CMD_CLE) 
     38#define NAND_WRITE_ADDR         (NAND_CMD_CS | NAND_CMD_ALE) 
     39#define NAND_WRITE_DATA         (NAND_CMD_CS) 
     40#define NAND_READ_DATA          (NAND_CMD_CS) 
     41#define NAND_WAIT_WR_C          (1 << 3) 
     42#define NAND_WAIT_RD            (0x1) 
     43 
     44#define ADDSEL1_MASK(x)         (x << 4) 
     45#define ADDSEL1_REGEN           1 
     46#define BUSCON1_SETUP           (1 << 22) 
     47#define BUSCON1_BCGEN_RES       (0x3 << 12) 
     48#define BUSCON1_WAITWRC2        (2 << 8) 
     49#define BUSCON1_WAITRDC2        (2 << 6) 
     50#define BUSCON1_HOLDC1          (1 << 4) 
     51#define BUSCON1_RECOVC1         (1 << 2) 
     52#define BUSCON1_CMULT4          1 
     53#define NAND_CON_NANDM          1 
     54#define NAND_CON_CSMUX          (1 << 1) 
     55#define NAND_CON_CS_P           (1 << 4) 
     56#define NAND_CON_SE_P           (1 << 5) 
     57#define NAND_CON_WP_P           (1 << 6) 
     58#define NAND_CON_PRE_P          (1 << 7) 
     59#define NAND_CON_IN_CS0         0 
     60#define NAND_CON_OUT_CS0        0 
     61#define NAND_CON_IN_CS1         (1 << 8) 
     62#define NAND_CON_OUT_CS1        (1 << 10) 
     63#define NAND_CON_CE             (1 << 20) 
     64 
     65#define NAND_BASE_ADDRESS       (KSEG1 | 0x14000000) 
     66 
     67static const char *part_probes[] = { "cmdlinepart", NULL }; 
     68 
     69static void 
     70xway_select_chip(struct mtd_info *mtd, int chip) 
     71{ 
     72        switch (chip) { 
     73        case -1: 
     74                ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON); 
     75                ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON); 
     76                break; 
     77        case 0: 
     78                ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON); 
     79                ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON); 
     80                /* reset the nand chip */ 
     81                while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); 
     82                ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD))); 
     83                break; 
     84        default: 
     85                BUG(); 
     86        } 
     87} 
     88 
     89static void 
     90xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) 
     91{ 
     92        struct nand_chip *this = mtd->priv; 
     93 
     94        if (ctrl & NAND_CTRL_CHANGE) { 
     95                if(ctrl & NAND_CLE) 
     96                        this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_CMD); 
     97                else if(ctrl & NAND_ALE) 
     98                        this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_ADDR); 
     99        } 
     100 
     101        if(data != NAND_CMD_NONE) { 
     102                *(volatile u8*)((u32)this->IO_ADDR_W) = data; 
     103                while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); 
     104        } 
     105} 
     106 
     107static int 
     108xway_dev_ready(struct mtd_info *mtd) 
     109{ 
     110        return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD; 
     111} 
     112 
     113void 
     114nand_write(unsigned int addr, unsigned int val) 
     115{ 
     116        ltq_w32(val, ((u32*)(NAND_BASE_ADDRESS | addr))); 
     117        while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); 
     118} 
     119 
     120unsigned char 
     121ltq_nand_read_byte(struct mtd_info *mtd) 
     122{ 
     123        return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); 
     124} 
     125 
     126int xway_nand_probe(struct platform_device *pdev) 
     127{ 
     128//      ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1"); 
     129        ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE"); 
     130        ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE"); 
     131        if (ltq_is_ar9() || ltq_is_vr9()) { 
     132                ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY"); 
     133                ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD"); 
     134        } 
     135 
     136        ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00) 
     137                | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1); 
     138 
     139        ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 
     140                | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 
     141                | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); 
     142 
     143        ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P 
     144                | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P 
     145                | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON); 
     146 
     147        ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD))); 
     148        while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); 
     149 
     150        return 0; 
     151} 
     152 
     153static struct platform_nand_data falcon_flash_nand_data = { 
     154        .chip = { 
     155                .nr_chips               = 1, 
     156                .chip_delay             = 30, 
     157                .part_probe_types       = part_probes, 
     158        }, 
     159        .ctrl = { 
     160                .probe          = xway_nand_probe, 
     161                .cmd_ctrl       = xway_cmd_ctrl, 
     162                .dev_ready      = xway_dev_ready, 
     163                .select_chip    = xway_select_chip, 
     164                .read_byte = ltq_nand_read_byte, 
     165        } 
     166}; 
     167 
     168static struct resource ltq_nand_res = 
     169        MEM_RES("nand", 0x14000000, 0x3ffffff); 
     170 
     171static struct platform_device ltq_flash_nand = { 
     172        .name           = "gen_nand", 
     173        .id             = -1, 
     174        .num_resources  = 1, 
     175        .resource       = &ltq_nand_res, 
     176        .dev            = { 
     177                .platform_data = &falcon_flash_nand_data, 
     178        }, 
     179}; 
     180 
     181void __init 
     182xway_register_nand(void) 
     183{ 
     184        platform_device_register(&ltq_flash_nand); 
     185} 
  • drivers/mtd/nand/plat_nand.c

    diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c
    index 633c04b..c3e3ef6 100644
    a b static int __devinit plat_nand_probe(struct platform_device *pdev) 
    7777        data->chip.select_chip = pdata->ctrl.select_chip; 
    7878        data->chip.write_buf = pdata->ctrl.write_buf; 
    7979        data->chip.read_buf = pdata->ctrl.read_buf; 
     80        data->chip.read_byte = pdata->ctrl.read_byte; 
    8081        data->chip.chip_delay = pdata->chip.chip_delay; 
    8182        data->chip.options |= pdata->chip.options; 
    8283 
  • include/linux/mtd/nand.h

    diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
    index c2b9ac4..597e1a0 100644
    a b struct platform_nand_ctrl { 
    656656        void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); 
    657657        void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 
    658658        void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 
     659        unsigned char (*read_byte)(struct mtd_info *mtd); 
    659660        void *priv; 
    660661}; 
    661662 
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