source: trunk/target/linux/lantiq/patches-3.3/0061-MIPS-adds-dsl-clocks.patch @ 31307

Last change on this file since 31307 was 31307, checked in by blogic, 4 years ago

[lantiq] adds 3.3 patches and files

File size: 2.2 KB
  • arch/mips/lantiq/xway/sysctrl.c

    From 77da4ad0d8dfe7c5f46a06296a04a992a961c1a3 Mon Sep 17 00:00:00 2001
    From: John Crispin <blogic@openwrt.org>
    Date: Tue, 20 Mar 2012 13:05:11 +0100
    Subject: [PATCH 61/70] MIPS: adds dsl clocks
    
    ---
     arch/mips/lantiq/xway/sysctrl.c |   15 +++++++++++++--
     1 files changed, 13 insertions(+), 2 deletions(-)
    
    diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
    index 6771a7e..3672fc6 100644
    a b  
    4141#define PMU_PCI         BIT(4) 
    4242#define PMU_DMA         BIT(5) 
    4343#define PMU_USB0        BIT(5) 
     44#define PMU_EPHY        BIT(7)  /* ase */ 
    4445#define PMU_SPI         BIT(8) 
    45 #define PMU_EPHY        BIT(7) 
     46#define PMU_DFE         BIT(9) 
    4647#define PMU_EBU         BIT(10) 
    4748#define PMU_STP         BIT(11) 
    4849#define PMU_GPT         BIT(12) 
    static int ltq_pci_ext_enable(struct clk *clk) 
    147148 
    148149static void ltq_pci_ext_disable(struct clk *clk) 
    149150{ 
    150         /* enable external pci clock */ 
     151        /* disable external pci clock (internal) */ 
    151152        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), 
    152153                CGU_IFCCR); 
    153154        ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR); 
    void __init ltq_soc_init(void) 
    246247                        clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); 
    247248                clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), 
    248249                clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); 
     250                clkdev_add_pmu("ltq_dsl", NULL, 0, 
     251                        PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 
     252                        PMU_AHBS | PMU_DFE); 
    249253        } else if (ltq_is_vr9()) { 
    250254                clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), 
    251255                        ltq_vr9_fpi_hz()); 
    void __init ltq_soc_init(void) 
    261265                        PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | 
    262266                        PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 
    263267                        PMU_PPE_QSB); 
     268                clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS); 
    264269        } else if (ltq_is_ar9()) { 
    265270                clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), 
    266271                        ltq_ar9_fpi_hz()); 
    267272                clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); 
     273                clkdev_add_pmu("ltq_dsl", NULL, 0, 
     274                        PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 
     275                        PMU_PPE_QSB | PMU_AHBS | PMU_DFE); 
    268276        } else { 
    269277                clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), 
    270278                        ltq_danube_io_region_clock()); 
     279                clkdev_add_pmu("ltq_dsl", NULL, 0, 
     280                        PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 
     281                        PMU_PPE_QSB | PMU_AHBS | PMU_DFE); 
    271282        } 
    272283} 
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