source: trunk/target/linux/lantiq/patches/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch @ 28721

Last change on this file since 28721 was 28721, checked in by blogic, 5 years ago

lantiq: bump to 3.1

File size: 32.0 KB
  • new file arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h

    From ff57bc17a9964d24708759c6d78a51e337563d5f Mon Sep 17 00:00:00 2001
    From: John Crispin <blogic@openwrt.org>
    Date: Thu, 11 Aug 2011 14:33:04 +0200
    Subject: [PATCH 06/24] MIPS: lantiq: add basic support for FALC-ON
    
    Adds support for the FALC-ON SoC. This SoC is from the fiber to the home GPON
    series.
    
    Signed-off-by: John Crispin <blogic@openwrt.org>
    Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
    Cc: linux-mips@linux-mips.org
    ---
     .../include/asm/mach-lantiq/falcon/falcon_irq.h    |  268 ++++++++++++++++++++
     arch/mips/include/asm/mach-lantiq/falcon/irq.h     |   18 ++
     .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |  140 ++++++++++
     arch/mips/include/asm/mach-lantiq/lantiq.h         |    1 +
     arch/mips/lantiq/Kconfig                           |    4 +
     arch/mips/lantiq/Makefile                          |    1 +
     arch/mips/lantiq/Platform                          |    1 +
     arch/mips/lantiq/falcon/Makefile                   |    1 +
     arch/mips/lantiq/falcon/clk.c                      |   44 ++++
     arch/mips/lantiq/falcon/devices.c                  |   87 +++++++
     arch/mips/lantiq/falcon/devices.h                  |   18 ++
     arch/mips/lantiq/falcon/prom.c                     |   72 ++++++
     arch/mips/lantiq/falcon/reset.c                    |   87 +++++++
     arch/mips/lantiq/falcon/sysctrl.c                  |  181 +++++++++++++
     14 files changed, 923 insertions(+), 0 deletions(-)
     create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
     create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h
     create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
     create mode 100644 arch/mips/lantiq/falcon/Makefile
     create mode 100644 arch/mips/lantiq/falcon/clk.c
     create mode 100644 arch/mips/lantiq/falcon/devices.c
     create mode 100644 arch/mips/lantiq/falcon/devices.h
     create mode 100644 arch/mips/lantiq/falcon/prom.c
     create mode 100644 arch/mips/lantiq/falcon/reset.c
     create mode 100644 arch/mips/lantiq/falcon/sysctrl.c
    
    - +  
     1/* 
     2 *  This program is free software; you can redistribute it and/or modify it 
     3 *  under the terms of the GNU General Public License version 2 as published 
     4 *  by the Free Software Foundation. 
     5 * 
     6 *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> 
     7 */ 
     8 
     9#ifndef _FALCON_IRQ__ 
     10#define _FALCON_IRQ__ 
     11 
     12#define INT_NUM_IRQ0                    8 
     13#define INT_NUM_IM0_IRL0                (INT_NUM_IRQ0 + 0) 
     14#define INT_NUM_IM1_IRL0                (INT_NUM_IM0_IRL0 + 32) 
     15#define INT_NUM_IM2_IRL0                (INT_NUM_IM1_IRL0 + 32) 
     16#define INT_NUM_IM3_IRL0                (INT_NUM_IM2_IRL0 + 32) 
     17#define INT_NUM_IM4_IRL0                (INT_NUM_IM3_IRL0 + 32) 
     18#define INT_NUM_EXTRA_START             (INT_NUM_IM4_IRL0 + 32) 
     19#define INT_NUM_IM_OFFSET               (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) 
     20 
     21#define MIPS_CPU_TIMER_IRQ                      7 
     22 
     23/* HOST IF Event Interrupt */ 
     24#define FALCON_IRQ_HOST                         (INT_NUM_IM0_IRL0 + 0) 
     25/* HOST IF Mailbox0 Receive Interrupt */ 
     26#define FALCON_IRQ_HOST_MB0_RX                  (INT_NUM_IM0_IRL0 + 1) 
     27/* HOST IF Mailbox0 Transmit Interrupt */ 
     28#define FALCON_IRQ_HOST_MB0_TX                  (INT_NUM_IM0_IRL0 + 2) 
     29/* HOST IF Mailbox1 Receive Interrupt */ 
     30#define FALCON_IRQ_HOST_MB1_RX                  (INT_NUM_IM0_IRL0 + 3) 
     31/* HOST IF Mailbox1 Transmit Interrupt */ 
     32#define FALCON_IRQ_HOST_MB1_TX                  (INT_NUM_IM0_IRL0 + 4) 
     33/* I2C Last Single Data Transfer Request */ 
     34#define FALCON_IRQ_I2C_LSREQ                    (INT_NUM_IM0_IRL0 + 8) 
     35/* I2C Single Data Transfer Request */ 
     36#define FALCON_IRQ_I2C_SREQ                     (INT_NUM_IM0_IRL0 + 9) 
     37/* I2C Last Burst Data Transfer Request */ 
     38#define FALCON_IRQ_I2C_LBREQ                    (INT_NUM_IM0_IRL0 + 10) 
     39/* I2C Burst Data Transfer Request */ 
     40#define FALCON_IRQ_I2C_BREQ                     (INT_NUM_IM0_IRL0 + 11) 
     41/* I2C Error Interrupt */ 
     42#define FALCON_IRQ_I2C_I2C_ERR                  (INT_NUM_IM0_IRL0 + 12) 
     43/* I2C Protocol Interrupt */ 
     44#define FALCON_IRQ_I2C_I2C_P                    (INT_NUM_IM0_IRL0 + 13) 
     45/* SSC Transmit Interrupt */ 
     46#define FALCON_IRQ_SSC_T                        (INT_NUM_IM0_IRL0 + 14) 
     47/* SSC Receive Interrupt */ 
     48#define FALCON_IRQ_SSC_R                        (INT_NUM_IM0_IRL0 + 15) 
     49/* SSC Error Interrupt */ 
     50#define FALCON_IRQ_SSC_E                        (INT_NUM_IM0_IRL0 + 16) 
     51/* SSC Frame Interrupt */ 
     52#define FALCON_IRQ_SSC_F                        (INT_NUM_IM0_IRL0 + 17) 
     53/* Advanced Encryption Standard Interrupt */ 
     54#define FALCON_IRQ_AES_AES                      (INT_NUM_IM0_IRL0 + 27) 
     55/* Secure Hash Algorithm Interrupt */ 
     56#define FALCON_IRQ_SHA_HASH                     (INT_NUM_IM0_IRL0 + 28) 
     57/* PCM Receive Interrupt */ 
     58#define FALCON_IRQ_PCM_RX                       (INT_NUM_IM0_IRL0 + 29) 
     59/* PCM Transmit Interrupt */ 
     60#define FALCON_IRQ_PCM_TX                       (INT_NUM_IM0_IRL0 + 30) 
     61/* PCM Transmit Crash Interrupt */ 
     62#define FALCON_IRQ_PCM_HW2_CRASH                (INT_NUM_IM0_IRL0 + 31) 
     63 
     64/* EBU Serial Flash Command Error */ 
     65#define FALCON_IRQ_EBU_SF_CMDERR                (INT_NUM_IM1_IRL0 + 0) 
     66/* EBU Serial Flash Command Overwrite Error */ 
     67#define FALCON_IRQ_EBU_SF_COVERR                (INT_NUM_IM1_IRL0 + 1) 
     68/* EBU Serial Flash Busy */ 
     69#define FALCON_IRQ_EBU_SF_BUSY                  (INT_NUM_IM1_IRL0 + 2) 
     70/* External Interrupt from GPIO P0 */ 
     71#define FALCON_IRQ_GPIO_P0                      (INT_NUM_IM1_IRL0 + 4) 
     72/* External Interrupt from GPIO P1 */ 
     73#define FALCON_IRQ_GPIO_P1                      (INT_NUM_IM1_IRL0 + 5) 
     74/* External Interrupt from GPIO P2 */ 
     75#define FALCON_IRQ_GPIO_P2                      (INT_NUM_IM1_IRL0 + 6) 
     76/* External Interrupt from GPIO P3 */ 
     77#define FALCON_IRQ_GPIO_P3                      (INT_NUM_IM1_IRL0 + 7) 
     78/* External Interrupt from GPIO P4 */ 
     79#define FALCON_IRQ_GPIO_P4                      (INT_NUM_IM1_IRL0 + 8) 
     80/* 8kHz backup interrupt derived from core-PLL */ 
     81#define FALCON_IRQ_FSC_BKP                      (INT_NUM_IM1_IRL0 + 10) 
     82/* FSC Timer Interrupt 0 */ 
     83#define FALCON_IRQ_FSCT_CMP0                    (INT_NUM_IM1_IRL0 + 11) 
     84/* FSC Timer Interrupt 1 */ 
     85#define FALCON_IRQ_FSCT_CMP1                    (INT_NUM_IM1_IRL0 + 12) 
     86/* 8kHz root interrupt derived from GPON interface */ 
     87#define FALCON_IRQ_FSC_ROOT                     (INT_NUM_IM1_IRL0 + 13) 
     88/* Time of Day */ 
     89#define FALCON_IRQ_TOD                          (INT_NUM_IM1_IRL0 + 14) 
     90/* PMA Interrupt from IntNode of the 200MHz Domain */ 
     91#define FALCON_IRQ_PMA_200M                     (INT_NUM_IM1_IRL0 + 15) 
     92/* PMA Interrupt from IntNode of the TX Clk Domain */ 
     93#define FALCON_IRQ_PMA_TX                       (INT_NUM_IM1_IRL0 + 16) 
     94/* PMA Interrupt from IntNode of the RX Clk Domain */ 
     95#define FALCON_IRQ_PMA_RX                       (INT_NUM_IM1_IRL0 + 17) 
     96/* SYS1 Interrupt */ 
     97#define FALCON_IRQ_SYS1                         (INT_NUM_IM1_IRL0 + 20) 
     98/* SYS GPE Interrupt */ 
     99#define FALCON_IRQ_SYS_GPE                      (INT_NUM_IM1_IRL0 + 21) 
     100/* Watchdog Access Error Interrupt */ 
     101#define FALCON_IRQ_WDT_AEIR                     (INT_NUM_IM1_IRL0 + 24) 
     102/* Watchdog Prewarning Interrupt */ 
     103#define FALCON_IRQ_WDT_PIR                      (INT_NUM_IM1_IRL0 + 25) 
     104/* SBIU interrupt */ 
     105#define FALCON_IRQ_SBIU0                        (INT_NUM_IM1_IRL0 + 27) 
     106/* FPI Bus Control Unit Interrupt */ 
     107#define FALCON_IRQ_BCU0                         (INT_NUM_IM1_IRL0 + 29) 
     108/* DDR Controller Interrupt */ 
     109#define FALCON_IRQ_DDR                          (INT_NUM_IM1_IRL0 + 30) 
     110/* Crossbar Error Interrupt */ 
     111#define FALCON_IRQ_XBAR_ERROR                   (INT_NUM_IM1_IRL0 + 31) 
     112 
     113/* ICTRLL 0 Interrupt */ 
     114#define FALCON_IRQ_ICTRLL0                      (INT_NUM_IM2_IRL0 + 0) 
     115/* ICTRLL 1 Interrupt */ 
     116#define FALCON_IRQ_ICTRLL1                      (INT_NUM_IM2_IRL0 + 1) 
     117/* ICTRLL 2 Interrupt */ 
     118#define FALCON_IRQ_ICTRLL2                      (INT_NUM_IM2_IRL0 + 2) 
     119/* ICTRLL 3 Interrupt */ 
     120#define FALCON_IRQ_ICTRLL3                      (INT_NUM_IM2_IRL0 + 3) 
     121/* OCTRLL 0 Interrupt */ 
     122#define FALCON_IRQ_OCTRLL0                      (INT_NUM_IM2_IRL0 + 4) 
     123/* OCTRLL 1 Interrupt */ 
     124#define FALCON_IRQ_OCTRLL1                      (INT_NUM_IM2_IRL0 + 5) 
     125/* OCTRLL 2 Interrupt */ 
     126#define FALCON_IRQ_OCTRLL2                      (INT_NUM_IM2_IRL0 + 6) 
     127/* OCTRLL 3 Interrupt */ 
     128#define FALCON_IRQ_OCTRLL3                      (INT_NUM_IM2_IRL0 + 7) 
     129/* OCTRLG Interrupt */ 
     130#define FALCON_IRQ_OCTRLG                       (INT_NUM_IM2_IRL0 + 9) 
     131/* IQM Interrupt */ 
     132#define FALCON_IRQ_IQM                          (INT_NUM_IM2_IRL0 + 10) 
     133/* FSQM Interrupt */ 
     134#define FALCON_IRQ_FSQM                         (INT_NUM_IM2_IRL0 + 11) 
     135/* TMU Interrupt */ 
     136#define FALCON_IRQ_TMU                          (INT_NUM_IM2_IRL0 + 12) 
     137/* LINK1 Interrupt */ 
     138#define FALCON_IRQ_LINK1                        (INT_NUM_IM2_IRL0 + 14) 
     139/* ICTRLC 0 Interrupt */ 
     140#define FALCON_IRQ_ICTRLC0                      (INT_NUM_IM2_IRL0 + 16) 
     141/* ICTRLC 1 Interrupt */ 
     142#define FALCON_IRQ_ICTRLC1                      (INT_NUM_IM2_IRL0 + 17) 
     143/* OCTRLC Interrupt */ 
     144#define FALCON_IRQ_OCTRLC                       (INT_NUM_IM2_IRL0 + 18) 
     145/* CONFIG Break Interrupt */ 
     146#define FALCON_IRQ_CONFIG_BREAK                 (INT_NUM_IM2_IRL0 + 19) 
     147/* CONFIG Interrupt */ 
     148#define FALCON_IRQ_CONFIG                       (INT_NUM_IM2_IRL0 + 20) 
     149/* Dispatcher Interrupt */ 
     150#define FALCON_IRQ_DISP                         (INT_NUM_IM2_IRL0 + 21) 
     151/* TBM Interrupt */ 
     152#define FALCON_IRQ_TBM                          (INT_NUM_IM2_IRL0 + 22) 
     153/* GTC Downstream Interrupt */ 
     154#define FALCON_IRQ_GTC_DS                       (INT_NUM_IM2_IRL0 + 29) 
     155/* GTC Upstream Interrupt */ 
     156#define FALCON_IRQ_GTC_US                       (INT_NUM_IM2_IRL0 + 30) 
     157/* EIM Interrupt */ 
     158#define FALCON_IRQ_EIM                          (INT_NUM_IM2_IRL0 + 31) 
     159 
     160/* ASC0 Transmit Interrupt */ 
     161#define FALCON_IRQ_ASC0_T                       (INT_NUM_IM3_IRL0 + 0) 
     162/* ASC0 Receive Interrupt */ 
     163#define FALCON_IRQ_ASC0_R                       (INT_NUM_IM3_IRL0 + 1) 
     164/* ASC0 Error Interrupt */ 
     165#define FALCON_IRQ_ASC0_E                       (INT_NUM_IM3_IRL0 + 2) 
     166/* ASC0 Transmit Buffer Interrupt */ 
     167#define FALCON_IRQ_ASC0_TB                      (INT_NUM_IM3_IRL0 + 3) 
     168/* ASC0 Autobaud Start Interrupt */ 
     169#define FALCON_IRQ_ASC0_ABST                    (INT_NUM_IM3_IRL0 + 4) 
     170/* ASC0 Autobaud Detection Interrupt */ 
     171#define FALCON_IRQ_ASC0_ABDET                   (INT_NUM_IM3_IRL0 + 5) 
     172/* ASC1 Modem Status Interrupt */ 
     173#define FALCON_IRQ_ASC0_MS                      (INT_NUM_IM3_IRL0 + 6) 
     174/* ASC0 Soft Flow Control Interrupt */ 
     175#define FALCON_IRQ_ASC0_SFC                     (INT_NUM_IM3_IRL0 + 7) 
     176/* ASC1 Transmit Interrupt */ 
     177#define FALCON_IRQ_ASC1_T                       (INT_NUM_IM3_IRL0 + 8) 
     178/* ASC1 Receive Interrupt */ 
     179#define FALCON_IRQ_ASC1_R                       (INT_NUM_IM3_IRL0 + 9) 
     180/* ASC1 Error Interrupt */ 
     181#define FALCON_IRQ_ASC1_E                       (INT_NUM_IM3_IRL0 + 10) 
     182/* ASC1 Transmit Buffer Interrupt */ 
     183#define FALCON_IRQ_ASC1_TB                      (INT_NUM_IM3_IRL0 + 11) 
     184/* ASC1 Autobaud Start Interrupt */ 
     185#define FALCON_IRQ_ASC1_ABST                    (INT_NUM_IM3_IRL0 + 12) 
     186/* ASC1 Autobaud Detection Interrupt */ 
     187#define FALCON_IRQ_ASC1_ABDET                   (INT_NUM_IM3_IRL0 + 13) 
     188/* ASC1 Modem Status Interrupt */ 
     189#define FALCON_IRQ_ASC1_MS                      (INT_NUM_IM3_IRL0 + 14) 
     190/* ASC1 Soft Flow Control Interrupt */ 
     191#define FALCON_IRQ_ASC1_SFC                     (INT_NUM_IM3_IRL0 + 15) 
     192/* GPTC Timer/Counter 1A Interrupt */ 
     193#define FALCON_IRQ_GPTC_TC1A                    (INT_NUM_IM3_IRL0 + 16) 
     194/* GPTC Timer/Counter 1B Interrupt */ 
     195#define FALCON_IRQ_GPTC_TC1B                    (INT_NUM_IM3_IRL0 + 17) 
     196/* GPTC Timer/Counter 2A Interrupt */ 
     197#define FALCON_IRQ_GPTC_TC2A                    (INT_NUM_IM3_IRL0 + 18) 
     198/* GPTC Timer/Counter 2B Interrupt */ 
     199#define FALCON_IRQ_GPTC_TC2B                    (INT_NUM_IM3_IRL0 + 19) 
     200/* GPTC Timer/Counter 3A Interrupt */ 
     201#define FALCON_IRQ_GPTC_TC3A                    (INT_NUM_IM3_IRL0 + 20) 
     202/* GPTC Timer/Counter 3B Interrupt */ 
     203#define FALCON_IRQ_GPTC_TC3B                    (INT_NUM_IM3_IRL0 + 21) 
     204/* DFEV0, Channel 1 Transmit Interrupt */ 
     205#define FALCON_IRQ_DFEV0_2TX                    (INT_NUM_IM3_IRL0 + 26) 
     206/* DFEV0, Channel 1 Receive Interrupt */ 
     207#define FALCON_IRQ_DFEV0_2RX                    (INT_NUM_IM3_IRL0 + 27) 
     208/* DFEV0, Channel 1 General Purpose Interrupt */ 
     209#define FALCON_IRQ_DFEV0_2GP                    (INT_NUM_IM3_IRL0 + 28) 
     210/* DFEV0, Channel 0 Transmit Interrupt */ 
     211#define FALCON_IRQ_DFEV0_1TX                    (INT_NUM_IM3_IRL0 + 29) 
     212/* DFEV0, Channel 0 Receive Interrupt */ 
     213#define FALCON_IRQ_DFEV0_1RX                    (INT_NUM_IM3_IRL0 + 30) 
     214/* DFEV0, Channel 0 General Purpose Interrupt */ 
     215#define FALCON_IRQ_DFEV0_1GP                    (INT_NUM_IM3_IRL0 + 31) 
     216 
     217/* ICTRLL 0 Error */ 
     218#define FALCON_IRQ_ICTRLL0_ERR                  (INT_NUM_IM4_IRL0 + 0) 
     219/* ICTRLL 1 Error */ 
     220#define FALCON_IRQ_ICTRLL1_ERR                  (INT_NUM_IM4_IRL0 + 1) 
     221/* ICTRLL 2 Error */ 
     222#define FALCON_IRQ_ICTRLL2_ERR                  (INT_NUM_IM4_IRL0 + 2) 
     223/* ICTRLL 3 Error */ 
     224#define FALCON_IRQ_ICTRLL3_ERR                  (INT_NUM_IM4_IRL0 + 3) 
     225/* OCTRLL 0 Error */ 
     226#define FALCON_IRQ_OCTRLL0_ERR                  (INT_NUM_IM4_IRL0 + 4) 
     227/* OCTRLL 1 Error */ 
     228#define FALCON_IRQ_OCTRLL1_ERR                  (INT_NUM_IM4_IRL0 + 5) 
     229/* OCTRLL 2 Error */ 
     230#define FALCON_IRQ_OCTRLL2_ERR                  (INT_NUM_IM4_IRL0 + 6) 
     231/* OCTRLL 3 Error */ 
     232#define FALCON_IRQ_OCTRLL3_ERR                  (INT_NUM_IM4_IRL0 + 7) 
     233/* ICTRLG Error */ 
     234#define FALCON_IRQ_ICTRLG_ERR                   (INT_NUM_IM4_IRL0 + 8) 
     235/* OCTRLG Error */ 
     236#define FALCON_IRQ_OCTRLG_ERR                   (INT_NUM_IM4_IRL0 + 9) 
     237/* IQM Error */ 
     238#define FALCON_IRQ_IQM_ERR                      (INT_NUM_IM4_IRL0 + 10) 
     239/* FSQM Error */ 
     240#define FALCON_IRQ_FSQM_ERR                     (INT_NUM_IM4_IRL0 + 11) 
     241/* TMU Error */ 
     242#define FALCON_IRQ_TMU_ERR                      (INT_NUM_IM4_IRL0 + 12) 
     243/* MPS Status Interrupt #0 (VPE1 to VPE0) */ 
     244#define FALCON_IRQ_MPS_IR0                      (INT_NUM_IM4_IRL0 + 14) 
     245/* MPS Status Interrupt #1 (VPE1 to VPE0) */ 
     246#define FALCON_IRQ_MPS_IR1                      (INT_NUM_IM4_IRL0 + 15) 
     247/* MPS Status Interrupt #2 (VPE1 to VPE0) */ 
     248#define FALCON_IRQ_MPS_IR2                      (INT_NUM_IM4_IRL0 + 16) 
     249/* MPS Status Interrupt #3 (VPE1 to VPE0) */ 
     250#define FALCON_IRQ_MPS_IR3                      (INT_NUM_IM4_IRL0 + 17) 
     251/* MPS Status Interrupt #4 (VPE1 to VPE0) */ 
     252#define FALCON_IRQ_MPS_IR4                      (INT_NUM_IM4_IRL0 + 18) 
     253/* MPS Status Interrupt #5 (VPE1 to VPE0) */ 
     254#define FALCON_IRQ_MPS_IR5                      (INT_NUM_IM4_IRL0 + 19) 
     255/* MPS Status Interrupt #6 (VPE1 to VPE0) */ 
     256#define FALCON_IRQ_MPS_IR6                      (INT_NUM_IM4_IRL0 + 20) 
     257/* MPS Status Interrupt #7 (VPE1 to VPE0) */ 
     258#define FALCON_IRQ_MPS_IR7                      (INT_NUM_IM4_IRL0 + 21) 
     259/* MPS Status Interrupt #8 (VPE1 to VPE0) */ 
     260#define FALCON_IRQ_MPS_IR8                      (INT_NUM_IM4_IRL0 + 22) 
     261/* VPE0 Exception Level Flag Interrupt */ 
     262#define FALCON_IRQ_VPE0_EXL                     (INT_NUM_IM4_IRL0 + 29) 
     263/* VPE0 Error Level Flag Interrupt */ 
     264#define FALCON_IRQ_VPE0_ERL                     (INT_NUM_IM4_IRL0 + 30) 
     265/* VPE0 Performance Monitoring Counter Interrupt */ 
     266#define FALCON_IRQ_VPE0_PMCIR                   (INT_NUM_IM4_IRL0 + 31) 
     267 
     268#endif /* _FALCON_IRQ__ */ 
  • new file arch/mips/include/asm/mach-lantiq/falcon/irq.h

    - +  
     1/* 
     2 *  This program is free software; you can redistribute it and/or modify it 
     3 *  under the terms of the GNU General Public License version 2 as published 
     4 *  by the Free Software Foundation. 
     5 * 
     6 *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> 
     7 */ 
     8 
     9#ifndef __FALCON_IRQ_H 
     10#define __FALCON_IRQ_H 
     11 
     12#include <falcon_irq.h> 
     13 
     14#define NR_IRQS 328 
     15 
     16#include_next <irq.h> 
     17 
     18#endif 
  • new file arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h

    - +  
     1/* 
     2 * This program is free software; you can redistribute it and/or modify it 
     3 * under the terms of the GNU General Public License version 2 as published 
     4 * by the Free Software Foundation. 
     5 * 
     6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org> 
     7 */ 
     8 
     9#ifndef _LTQ_FALCON_H__ 
     10#define _LTQ_FALCON_H__ 
     11 
     12#ifdef CONFIG_SOC_FALCON 
     13 
     14#include <lantiq.h> 
     15 
     16/* Chip IDs */ 
     17#define SOC_ID_FALCON           0x01B8 
     18 
     19/* SoC Types */ 
     20#define SOC_TYPE_FALCON         0x01 
     21 
     22/* ASC0/1 - serial port */ 
     23#define LTQ_ASC0_BASE_ADDR      0x1E100C00 
     24#define LTQ_ASC1_BASE_ADDR      0x1E100B00 
     25#define LTQ_ASC_SIZE            0x100 
     26 
     27#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8)) 
     28#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1) 
     29#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2) 
     30 
     31/* during early_printk no ioremap possible at this early stage 
     32   lets use KSEG1 instead  */ 
     33#define LTQ_EARLY_ASC           KSEG1ADDR(LTQ_ASC0_BASE_ADDR) 
     34 
     35/* ICU - interrupt control unit */ 
     36#define LTQ_ICU_BASE_ADDR       0x1F880200 
     37#define LTQ_ICU_SIZE            0x100 
     38 
     39/* WDT */ 
     40#define LTQ_WDT_BASE_ADDR       0x1F8803F0 
     41#define LTQ_WDT_SIZE            0x10 
     42 
     43#define LTQ_RST_CAUSE_WDTRST    0x0002 
     44 
     45/* EBU - external bus unit */ 
     46#define LTQ_EBU_BASE_ADDR       0x18000000 
     47#define LTQ_EBU_SIZE            0x0100 
     48 
     49#define LTQ_EBU_MODCON  0x000C 
     50 
     51/* GPIO */ 
     52#define LTQ_GPIO0_BASE_ADDR     0x1D810000 
     53#define LTQ_GPIO0_SIZE          0x0080 
     54#define LTQ_GPIO1_BASE_ADDR     0x1E800100 
     55#define LTQ_GPIO1_SIZE          0x0080 
     56#define LTQ_GPIO2_BASE_ADDR     0x1D810100 
     57#define LTQ_GPIO2_SIZE          0x0080 
     58#define LTQ_GPIO3_BASE_ADDR     0x1E800200 
     59#define LTQ_GPIO3_SIZE          0x0080 
     60#define LTQ_GPIO4_BASE_ADDR     0x1E800300 
     61#define LTQ_GPIO4_SIZE          0x0080 
     62#define LTQ_PADCTRL0_BASE_ADDR  0x1DB01000 
     63#define LTQ_PADCTRL0_SIZE       0x0100 
     64#define LTQ_PADCTRL1_BASE_ADDR  0x1E800400 
     65#define LTQ_PADCTRL1_SIZE       0x0100 
     66#define LTQ_PADCTRL2_BASE_ADDR  0x1DB02000 
     67#define LTQ_PADCTRL2_SIZE       0x0100 
     68#define LTQ_PADCTRL3_BASE_ADDR  0x1E800500 
     69#define LTQ_PADCTRL3_SIZE       0x0100 
     70#define LTQ_PADCTRL4_BASE_ADDR  0x1E800600 
     71#define LTQ_PADCTRL4_SIZE       0x0100 
     72 
     73/* CHIP ID */ 
     74#define LTQ_STATUS_BASE_ADDR    0x1E802000 
     75 
     76#define LTQ_FALCON_CHIPID       ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) 
     77#define LTQ_FALCON_CHIPCONF     ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) 
     78 
     79/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ 
     80#define LTQ_SYS1_BASE_ADDR      0x1EF00000 
     81#define LTQ_SYS1_SIZE           0x0100 
     82#define LTQ_STATUS_BASE_ADDR    0x1E802000 
     83#define LTQ_STATUS_SIZE         0x0080 
     84#define LTQ_SYS_ETH_BASE_ADDR   0x1DB00000 
     85#define LTQ_SYS_ETH_SIZE        0x0100 
     86#define LTQ_SYS_GPE_BASE_ADDR   0x1D700000 
     87#define LTQ_SYS_GPE_SIZE        0x0100 
     88 
     89#define SYSCTL_SYS1             0 
     90#define SYSCTL_SYSETH           1 
     91#define SYSCTL_SYSGPE           2 
     92 
     93/* Activation Status Register */ 
     94#define ACTS_ASC1_ACT   0x00000800 
     95#define ACTS_P0         0x00010000 
     96#define ACTS_P1         0x00010000 
     97#define ACTS_P2         0x00020000 
     98#define ACTS_P3         0x00020000 
     99#define ACTS_P4         0x00040000 
     100#define ACTS_PADCTRL0   0x00100000 
     101#define ACTS_PADCTRL1   0x00100000 
     102#define ACTS_PADCTRL2   0x00200000 
     103#define ACTS_PADCTRL3   0x00200000 
     104#define ACTS_PADCTRL4   0x00400000 
     105 
     106extern void ltq_sysctl_activate(int module, unsigned int mask); 
     107extern void ltq_sysctl_deactivate(int module, unsigned int mask); 
     108extern void ltq_sysctl_clken(int module, unsigned int mask); 
     109extern void ltq_sysctl_clkdis(int module, unsigned int mask); 
     110extern void ltq_sysctl_reboot(int module, unsigned int mask); 
     111extern int ltq_gpe_is_activated(unsigned int mask); 
     112 
     113/* global register ranges */ 
     114extern __iomem void *ltq_ebu_membase; 
     115extern __iomem void *ltq_sys1_membase; 
     116#define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y)) 
     117#define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x)) 
     118#define ltq_ebu_w32_mask(clear, set, reg)   \ 
     119        ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg) 
     120 
     121#define ltq_sys1_w32(x, y)      ltq_w32((x), ltq_sys1_membase + (y)) 
     122#define ltq_sys1_r32(x)         ltq_r32(ltq_sys1_membase + (x)) 
     123#define ltq_sys1_w32_mask(clear, set, reg)   \ 
     124        ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) 
     125 
     126/* gpio_request wrapper to help configure the pin */ 
     127extern int ltq_gpio_request(unsigned int pin, unsigned int val, 
     128                                unsigned int dir, const char *name); 
     129extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); 
     130 
     131/* to keep the irq code generic we need to define these to 0 as falcon 
     132   has no EIU/EBU */ 
     133#define LTQ_EIU_BASE_ADDR       0 
     134#define LTQ_EBU_PCC_ISTAT       0 
     135 
     136#define ltq_is_ar9()    0 
     137#define ltq_is_vr9()    0 
     138 
     139#endif /* CONFIG_SOC_FALCON */ 
     140#endif /* _LTQ_XWAY_H__ */ 
  • arch/mips/include/asm/mach-lantiq/lantiq.h

    a b extern unsigned int ltq_get_soc_type(voi 
    2525/* clock speeds */ 
    2626#define CLOCK_60M       60000000 
    2727#define CLOCK_83M       83333333 
     28#define CLOCK_100M      100000000 
    2829#define CLOCK_111M      111111111 
    2930#define CLOCK_133M      133333333 
    3031#define CLOCK_167M      166666667 
  • arch/mips/lantiq/Kconfig

    a b config SOC_XWAY 
    1616        bool "XWAY" 
    1717        select SOC_TYPE_XWAY 
    1818        select HW_HAS_PCI 
     19 
     20config SOC_FALCON 
     21        bool "FALCON" 
    1922endchoice 
    2023 
    2124source "arch/mips/lantiq/xway/Kconfig" 
     25source "arch/mips/lantiq/falcon/Kconfig" 
    2226 
    2327endif 
  • arch/mips/lantiq/Makefile

    a b obj-y := irq.o setup.o clk.o prom.o devi 
    99obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 
    1010 
    1111obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ 
     12obj-$(CONFIG_SOC_FALCON) += falcon/ 
  • arch/mips/lantiq/Platform

    a b platform-$(CONFIG_LANTIQ) += lantiq/ 
    66cflags-$(CONFIG_LANTIQ)         += -I$(srctree)/arch/mips/include/asm/mach-lantiq 
    77load-$(CONFIG_LANTIQ)           = 0xffffffff80002000 
    88cflags-$(CONFIG_SOC_TYPE_XWAY)  += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway 
     9cflags-$(CONFIG_SOC_FALCON)     += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon 
  • new file arch/mips/lantiq/falcon/Makefile

    - +  
     1obj-y := clk.o prom.o reset.o sysctrl.o devices.o 
  • new file arch/mips/lantiq/falcon/clk.c

    - +  
     1/* 
     2 * This program is free software; you can redistribute it and/or modify it 
     3 * under the terms of the GNU General Public License version 2 as published 
     4 * by the Free Software Foundation. 
     5 * 
     6 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> 
     7 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 
     8 */ 
     9 
     10#include <linux/ioport.h> 
     11#include <linux/module.h> 
     12 
     13#include <lantiq_soc.h> 
     14 
     15#include "devices.h" 
     16 
     17/* CPU0 Clock Control Register */ 
     18#define LTQ_SYS1_CPU0CC         0x0040 
     19/* clock divider bit */ 
     20#define LTQ_CPU0CC_CPUDIV       0x0001 
     21 
     22unsigned int 
     23ltq_get_io_region_clock(void) 
     24{ 
     25        return CLOCK_200M; 
     26} 
     27EXPORT_SYMBOL(ltq_get_io_region_clock); 
     28 
     29unsigned int 
     30ltq_get_cpu_hz(void) 
     31{ 
     32        if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) 
     33                return CLOCK_200M; 
     34        else 
     35                return CLOCK_400M; 
     36} 
     37EXPORT_SYMBOL(ltq_get_cpu_hz); 
     38 
     39unsigned int 
     40ltq_get_fpi_hz(void) 
     41{ 
     42        return CLOCK_100M; 
     43} 
     44EXPORT_SYMBOL(ltq_get_fpi_hz); 
  • new file arch/mips/lantiq/falcon/devices.c

    - +  
     1/* 
     2 * This program is free software; you can redistribute it and/or modify it 
     3 * under the terms of the GNU General Public License version 2 as published 
     4 * by the Free Software Foundation. 
     5 * 
     6 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> 
     7 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 
     8 */ 
     9 
     10#include <linux/platform_device.h> 
     11#include <linux/mtd/nand.h> 
     12 
     13#include <lantiq_soc.h> 
     14 
     15#include "devices.h" 
     16 
     17/* nand flash */ 
     18/* address lines used for NAND control signals */ 
     19#define NAND_ADDR_ALE           0x10000 
     20#define NAND_ADDR_CLE           0x20000 
     21/* Ready/Busy Status */ 
     22#define MODCON_STS              0x0002 
     23/* Ready/Busy Status Edge */ 
     24#define MODCON_STSEDGE          0x0004 
     25 
     26static const char *part_probes[] = { "cmdlinepart", NULL }; 
     27 
     28static int 
     29falcon_nand_ready(struct mtd_info *mtd) 
     30{ 
     31        u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON); 
     32 
     33        return (((modcon & (MODCON_STS | MODCON_STSEDGE)) == 
     34                                                (MODCON_STS | MODCON_STSEDGE))); 
     35} 
     36 
     37static void 
     38falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) 
     39{ 
     40        struct nand_chip *this = mtd->priv; 
     41        unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; 
     42 
     43        if (ctrl & NAND_CTRL_CHANGE) { 
     44                nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE); 
     45 
     46                if (ctrl & NAND_CLE) 
     47                        nandaddr |= NAND_ADDR_CLE; 
     48                if (ctrl & NAND_ALE) 
     49                        nandaddr |= NAND_ADDR_ALE; 
     50 
     51                this->IO_ADDR_W = (void __iomem *) nandaddr; 
     52        } 
     53 
     54        if (cmd != NAND_CMD_NONE) 
     55                writeb(cmd, this->IO_ADDR_W); 
     56} 
     57 
     58static struct platform_nand_data falcon_flash_nand_data = { 
     59        .chip = { 
     60                .nr_chips               = 1, 
     61                .chip_delay             = 25, 
     62                .part_probe_types       = part_probes, 
     63        }, 
     64        .ctrl = { 
     65                .cmd_ctrl               = falcon_hwcontrol, 
     66                .dev_ready              = falcon_nand_ready, 
     67        } 
     68}; 
     69 
     70static struct resource ltq_nand_res = 
     71        MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX); 
     72 
     73static struct platform_device ltq_flash_nand = { 
     74        .name           = "gen_nand", 
     75        .id             = -1, 
     76        .num_resources  = 1, 
     77        .resource       = &ltq_nand_res, 
     78        .dev            = { 
     79                .platform_data = &falcon_flash_nand_data, 
     80        }, 
     81}; 
     82 
     83void __init 
     84falcon_register_nand(void) 
     85{ 
     86        platform_device_register(&ltq_flash_nand); 
     87} 
  • new file arch/mips/lantiq/falcon/devices.h

    - +  
     1/* 
     2 * This program is free software; you can redistribute it and/or modify 
     3 * it under the terms of the GNU General Public License as published by 
     4 * the Free Software Foundation; either version 2 of the License, or 
     5 * (at your option) any later version. 
     6 * 
     7 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> 
     8 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 
     9 */ 
     10 
     11#ifndef _FALCON_DEVICES_H__ 
     12#define _FALCON_DEVICES_H__ 
     13 
     14#include "../devices.h" 
     15 
     16extern void falcon_register_nand(void); 
     17 
     18#endif 
  • new file arch/mips/lantiq/falcon/prom.c

    - +  
     1/* 
     2 * This program is free software; you can redistribute it and/or modify it 
     3 * under the terms of the GNU General Public License version 2 as published 
     4 * by the Free Software Foundation. 
     5 * 
     6 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> 
     7 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 
     8 */ 
     9 
     10#include <lantiq_soc.h> 
     11 
     12#include "devices.h" 
     13 
     14#include "../prom.h" 
     15 
     16#define SOC_FALCON              "Falcon" 
     17 
     18#define PART_SHIFT      12 
     19#define PART_MASK       0x0FFFF000 
     20#define REV_SHIFT       28 
     21#define REV_MASK        0xF0000000 
     22#define SREV_SHIFT      22 
     23#define SREV_MASK       0x03C00000 
     24 
     25#define MUXC_SIF_RX_PIN         112 
     26#define MUXC_SIF_TX_PIN         113 
     27 
     28/* this parameter allows us enable/disable asc1 via commandline */ 
     29static int register_asc1; 
     30static int __init 
     31ltq_parse_asc1(char *p) 
     32{ 
     33        register_asc1 = 1; 
     34        return 0; 
     35} 
     36__setup("use_asc1", ltq_parse_asc1); 
     37 
     38void __init 
     39ltq_soc_setup(void) 
     40{ 
     41        ltq_register_asc(0); 
     42        ltq_register_wdt(); 
     43        falcon_register_gpio(); 
     44        if (register_asc1) { 
     45                ltq_register_asc(1); 
     46                if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx")) 
     47                        pr_err("failed to request asc1-rx"); 
     48                if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx")) 
     49                        pr_err("failed to request asc1-tx"); 
     50                ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT); 
     51        } 
     52} 
     53 
     54void __init 
     55ltq_soc_detect(struct ltq_soc_info *i) 
     56{ 
     57        i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; 
     58        i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; 
     59        i->srev = (ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT; 
     60        sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), 
     61                i->rev & 0x7, i->srev & 0x3); 
     62        switch (i->partnum) { 
     63        case SOC_ID_FALCON: 
     64                i->name = SOC_FALCON; 
     65                i->type = SOC_TYPE_FALCON; 
     66                break; 
     67 
     68        default: 
     69                unreachable(); 
     70                break; 
     71        } 
     72} 
  • new file arch/mips/lantiq/falcon/reset.c

    - +  
     1/* 
     2 * This program is free software; you can redistribute it and/or modify it 
     3 * under the terms of the GNU General Public License version 2 as published 
     4 * by the Free Software Foundation. 
     5 * 
     6 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> 
     7 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 
     8 */ 
     9 
     10#include <linux/init.h> 
     11#include <linux/io.h> 
     12#include <linux/pm.h> 
     13#include <asm/reboot.h> 
     14#include <linux/module.h> 
     15 
     16#include <lantiq_soc.h> 
     17 
     18/* CPU0 Reset Source Register */ 
     19#define LTQ_SYS1_CPU0RS         0x0040 
     20/* reset cause mask */ 
     21#define LTQ_CPU0RS_MASK         0x0003 
     22 
     23int 
     24ltq_reset_cause(void) 
     25{ 
     26        return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK; 
     27} 
     28EXPORT_SYMBOL_GPL(ltq_reset_cause); 
     29 
     30#define BOOT_REG_BASE   (KSEG1 | 0x1F200000) 
     31#define BOOT_PW1_REG    (BOOT_REG_BASE | 0x20) 
     32#define BOOT_PW2_REG    (BOOT_REG_BASE | 0x24) 
     33#define BOOT_PW1        0x4C545100 
     34#define BOOT_PW2        0x0051544C 
     35 
     36#define WDT_REG_BASE    (KSEG1 | 0x1F8803F0) 
     37#define WDT_PW1         0x00BE0000 
     38#define WDT_PW2         0x00DC0000 
     39 
     40static void 
     41ltq_machine_restart(char *command) 
     42{ 
     43        pr_notice("System restart\n"); 
     44        local_irq_disable(); 
     45 
     46        /* reboot magic */ 
     47        ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ 
     48        ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ 
     49        ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ 
     50 
     51        /* watchdog magic */ 
     52        ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); 
     53        ltq_w32(WDT_PW2 | 
     54                (0x3 << 26) | /* PWL */ 
     55                (0x2 << 24) | /* CLKDIV */ 
     56                (0x1 << 31) | /* enable */ 
     57                (1), /* reload */ 
     58                (void *)WDT_REG_BASE); 
     59        unreachable(); 
     60} 
     61 
     62static void 
     63ltq_machine_halt(void) 
     64{ 
     65        pr_notice("System halted.\n"); 
     66        local_irq_disable(); 
     67        unreachable(); 
     68} 
     69 
     70static void 
     71ltq_machine_power_off(void) 
     72{ 
     73        pr_notice("Please turn off the power now.\n"); 
     74        local_irq_disable(); 
     75        unreachable(); 
     76} 
     77 
     78static int __init 
     79mips_reboot_setup(void) 
     80{ 
     81        _machine_restart = ltq_machine_restart; 
     82        _machine_halt = ltq_machine_halt; 
     83        pm_power_off = ltq_machine_power_off; 
     84        return 0; 
     85} 
     86 
     87arch_initcall(mips_reboot_setup); 
  • new file arch/mips/lantiq/falcon/sysctrl.c

    - +  
     1/* 
     2 * This program is free software; you can redistribute it and/or modify it 
     3 * under the terms of the GNU General Public License version 2 as published 
     4 * by the Free Software Foundation. 
     5 * 
     6 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> 
     7 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 
     8 */ 
     9 
     10#include <linux/ioport.h> 
     11#include <asm/delay.h> 
     12 
     13#include <lantiq_soc.h> 
     14 
     15#include "devices.h" 
     16 
     17/* infrastructure control register */ 
     18#define SYS1_INFRAC             0x00bc 
     19/* Configuration fuses for drivers and pll */ 
     20#define STATUS_CONFIG           0x0040 
     21 
     22/* GPE frequency selection */ 
     23#define GPPC_OFFSET             24 
     24#define GPEFREQ_MASK            0x00000C0 
     25#define GPEFREQ_OFFSET          10 
     26/* Clock status register */ 
     27#define LTQ_SYSCTL_CLKS         0x0000 
     28/* Clock enable register */ 
     29#define LTQ_SYSCTL_CLKEN        0x0004 
     30/* Clock clear register */ 
     31#define LTQ_SYSCTL_CLKCLR       0x0008 
     32/* Activation Status Register */ 
     33#define LTQ_SYSCTL_ACTS         0x0020 
     34/* Activation Register */ 
     35#define LTQ_SYSCTL_ACT          0x0024 
     36/* Deactivation Register */ 
     37#define LTQ_SYSCTL_DEACT        0x0028 
     38/* reboot Register */ 
     39#define LTQ_SYSCTL_RBT          0x002c 
     40 
     41static struct resource ltq_sysctl_res[] = { 
     42        MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), 
     43        MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE), 
     44        MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE), 
     45}; 
     46 
     47static struct resource ltq_status_res = 
     48        MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE); 
     49static struct resource ltq_ebu_res = 
     50        MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); 
     51 
     52static void __iomem *ltq_sysctl[3]; 
     53static void __iomem *ltq_status_membase; 
     54void __iomem *ltq_sys1_membase; 
     55void __iomem *ltq_ebu_membase; 
     56 
     57#define ltq_reg_w32(m, x, y)    ltq_w32((x), ltq_sysctl[m] + (y)) 
     58#define ltq_reg_r32(m, x)       ltq_r32(ltq_sysctl[m] + (x)) 
     59#define ltq_reg_w32_mask(m, clear, set, reg)    \ 
     60                ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg) 
     61 
     62#define ltq_status_w32(x, y)    ltq_w32((x), ltq_status_membase + (y)) 
     63#define ltq_status_r32(x)       ltq_r32(ltq_status_membase + (x)) 
     64 
     65static inline void 
     66ltq_sysctl_wait(int module, unsigned int mask, unsigned int test) 
     67{ 
     68        int err = 1000000; 
     69 
     70        do {} while (--err && ((ltq_reg_r32(module, LTQ_SYSCTL_ACTS) 
     71                                        & mask) != test)); 
     72        if (!err) 
     73                pr_err("module de/activation failed %d %08X %08X\n", 
     74                                                        module, mask, test); 
     75} 
     76 
     77void 
     78ltq_sysctl_activate(int module, unsigned int mask) 
     79{ 
     80        if (module > SYSCTL_SYSGPE) 
     81                return; 
     82 
     83        ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); 
     84        ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT); 
     85        ltq_sysctl_wait(module, mask, mask); 
     86} 
     87EXPORT_SYMBOL(ltq_sysctl_activate); 
     88 
     89void 
     90ltq_sysctl_deactivate(int module, unsigned int mask) 
     91{ 
     92        if (module > SYSCTL_SYSGPE) 
     93                return; 
     94 
     95        ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); 
     96        ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT); 
     97        ltq_sysctl_wait(module, mask, 0); 
     98} 
     99EXPORT_SYMBOL(ltq_sysctl_deactivate); 
     100 
     101void 
     102ltq_sysctl_clken(int module, unsigned int mask) 
     103{ 
     104        if (module > SYSCTL_SYSGPE) 
     105                return; 
     106 
     107        ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); 
     108        ltq_sysctl_wait(module, mask, mask); 
     109} 
     110EXPORT_SYMBOL(ltq_sysctl_clken); 
     111 
     112void 
     113ltq_sysctl_clkdis(int module, unsigned int mask) 
     114{ 
     115        if (module > SYSCTL_SYSGPE) 
     116                return; 
     117 
     118        ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); 
     119        ltq_sysctl_wait(module, mask, 0); 
     120} 
     121EXPORT_SYMBOL(ltq_sysctl_clkdis); 
     122 
     123void 
     124ltq_sysctl_reboot(int module, unsigned int mask) 
     125{ 
     126        unsigned int act; 
     127 
     128        if (module > SYSCTL_SYSGPE) 
     129                return; 
     130 
     131        act = ltq_reg_r32(module, LTQ_SYSCTL_ACT); 
     132        if ((~act & mask) != 0) 
     133                ltq_sysctl_activate(module, ~act & mask); 
     134        ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT); 
     135        ltq_sysctl_wait(module, mask, mask); 
     136} 
     137EXPORT_SYMBOL(ltq_sysctl_reboot); 
     138 
     139/* enable the ONU core */ 
     140static void 
     141ltq_gpe_enable(void) 
     142{ 
     143        unsigned int freq; 
     144        unsigned int status; 
     145 
     146        /* if if the clock is already enabled */ 
     147        status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC); 
     148        if (status & (1 << (GPPC_OFFSET + 1))) 
     149                return; 
     150 
     151        if (ltq_status_r32(STATUS_CONFIG) == 0) 
     152                freq = 1; /* use 625MHz on unfused chip */ 
     153        else 
     154                freq = (ltq_status_r32(STATUS_CONFIG) & 
     155                        GPEFREQ_MASK) >> 
     156                        GPEFREQ_OFFSET; 
     157 
     158        /* apply new frequency */ 
     159        ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), 
     160                freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); 
     161        udelay(1); 
     162 
     163        /* enable new frequency */ 
     164        ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); 
     165        udelay(1); 
     166} 
     167 
     168void __init 
     169ltq_soc_init(void) 
     170{ 
     171        int i; 
     172 
     173        for (i = 0; i < 3; i++) 
     174                ltq_sysctl[i] = ltq_remap_resource(&ltq_sysctl_res[i]); 
     175 
     176        ltq_sys1_membase = ltq_sysctl[0]; 
     177        ltq_status_membase = ltq_remap_resource(&ltq_status_res); 
     178        ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res); 
     179 
     180        ltq_gpe_enable(); 
     181} 
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