source:
trunk/target/linux/octeon/patches2.6.30/005register_defs_octeon_mgmt.patch
@
19513
Last change on this file since 19513 was 19513, checked in by florian, 7 years ago  

File size: 48.4 KB 

new file arch/mips/include/asm/octeon/cvmxagldefs.h
The MGMT ethernet driver uses the AGL, MIXX and SMIX blocks, so we add definitions for them. Signedoffby: David Daney <ddaney@caviumnetworks.com>  arch/mips/include/asm/octeon/cvmxagldefs.h  1194 +++++++++++++++++++++++++ arch/mips/include/asm/octeon/cvmxmixxdefs.h  248 +++++ arch/mips/include/asm/octeon/cvmxsmixdefs.h  178 ++++ 3 files changed, 1620 insertions(+), 0 deletions() create mode 100644 arch/mips/include/asm/octeon/cvmxagldefs.h create mode 100644 arch/mips/include/asm/octeon/cvmxmixxdefs.h create mode 100644 arch/mips/include/asm/octeon/cvmxsmixdefs.h
 + 1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 20032008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * ASIS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 021101301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_AGL_DEFS_H__ 29 #define __CVMX_AGL_DEFS_H__ 30 31 #define CVMX_AGL_GMX_BAD_REG \ 32 CVMX_ADD_IO_SEG(0x00011800E0000518ull) 33 #define CVMX_AGL_GMX_BIST \ 34 CVMX_ADD_IO_SEG(0x00011800E0000400ull) 35 #define CVMX_AGL_GMX_DRV_CTL \ 36 CVMX_ADD_IO_SEG(0x00011800E00007F0ull) 37 #define CVMX_AGL_GMX_INF_MODE \ 38 CVMX_ADD_IO_SEG(0x00011800E00007F8ull) 39 #define CVMX_AGL_GMX_PRTX_CFG(offset) \ 40 CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048)) 41 #define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \ 42 CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048)) 43 #define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \ 44 CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048)) 45 #define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \ 46 CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048)) 47 #define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \ 48 CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048)) 49 #define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \ 50 CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048)) 51 #define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \ 52 CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048)) 53 #define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \ 54 CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048)) 55 #define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \ 56 CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048)) 57 #define CVMX_AGL_GMX_RXX_DECISION(offset) \ 58 CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048)) 59 #define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \ 60 CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048)) 61 #define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \ 62 CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048)) 63 #define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \ 64 CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048)) 65 #define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \ 66 CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048)) 67 #define CVMX_AGL_GMX_RXX_IFG(offset) \ 68 CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048)) 69 #define CVMX_AGL_GMX_RXX_INT_EN(offset) \ 70 CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048)) 71 #define CVMX_AGL_GMX_RXX_INT_REG(offset) \ 72 CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048)) 73 #define CVMX_AGL_GMX_RXX_JABBER(offset) \ 74 CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048)) 75 #define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \ 76 CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048)) 77 #define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \ 78 CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048)) 79 #define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \ 80 CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048)) 81 #define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \ 82 CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048)) 83 #define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \ 84 CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048)) 85 #define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \ 86 CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048)) 87 #define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \ 88 CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048)) 89 #define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \ 90 CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048)) 91 #define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \ 92 CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048)) 93 #define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \ 94 CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048)) 95 #define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \ 96 CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048)) 97 #define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \ 98 CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048)) 99 #define CVMX_AGL_GMX_RX_BP_DROPX(offset) \ 100 CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8)) 101 #define CVMX_AGL_GMX_RX_BP_OFFX(offset) \ 102 CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8)) 103 #define CVMX_AGL_GMX_RX_BP_ONX(offset) \ 104 CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8)) 105 #define CVMX_AGL_GMX_RX_PRT_INFO \ 106 CVMX_ADD_IO_SEG(0x00011800E00004E8ull) 107 #define CVMX_AGL_GMX_RX_TX_STATUS \ 108 CVMX_ADD_IO_SEG(0x00011800E00007E8ull) 109 #define CVMX_AGL_GMX_SMACX(offset) \ 110 CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048)) 111 #define CVMX_AGL_GMX_STAT_BP \ 112 CVMX_ADD_IO_SEG(0x00011800E0000520ull) 113 #define CVMX_AGL_GMX_TXX_APPEND(offset) \ 114 CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048)) 115 #define CVMX_AGL_GMX_TXX_CTL(offset) \ 116 CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048)) 117 #define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \ 118 CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048)) 119 #define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \ 120 CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048)) 121 #define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \ 122 CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048)) 123 #define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \ 124 CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048)) 125 #define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \ 126 CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048)) 127 #define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \ 128 CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048)) 129 #define CVMX_AGL_GMX_TXX_STAT0(offset) \ 130 CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048)) 131 #define CVMX_AGL_GMX_TXX_STAT1(offset) \ 132 CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048)) 133 #define CVMX_AGL_GMX_TXX_STAT2(offset) \ 134 CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048)) 135 #define CVMX_AGL_GMX_TXX_STAT3(offset) \ 136 CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048)) 137 #define CVMX_AGL_GMX_TXX_STAT4(offset) \ 138 CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048)) 139 #define CVMX_AGL_GMX_TXX_STAT5(offset) \ 140 CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048)) 141 #define CVMX_AGL_GMX_TXX_STAT6(offset) \ 142 CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048)) 143 #define CVMX_AGL_GMX_TXX_STAT7(offset) \ 144 CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048)) 145 #define CVMX_AGL_GMX_TXX_STAT8(offset) \ 146 CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048)) 147 #define CVMX_AGL_GMX_TXX_STAT9(offset) \ 148 CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048)) 149 #define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \ 150 CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048)) 151 #define CVMX_AGL_GMX_TXX_THRESH(offset) \ 152 CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048)) 153 #define CVMX_AGL_GMX_TX_BP \ 154 CVMX_ADD_IO_SEG(0x00011800E00004D0ull) 155 #define CVMX_AGL_GMX_TX_COL_ATTEMPT \ 156 CVMX_ADD_IO_SEG(0x00011800E0000498ull) 157 #define CVMX_AGL_GMX_TX_IFG \ 158 CVMX_ADD_IO_SEG(0x00011800E0000488ull) 159 #define CVMX_AGL_GMX_TX_INT_EN \ 160 CVMX_ADD_IO_SEG(0x00011800E0000508ull) 161 #define CVMX_AGL_GMX_TX_INT_REG \ 162 CVMX_ADD_IO_SEG(0x00011800E0000500ull) 163 #define CVMX_AGL_GMX_TX_JAM \ 164 CVMX_ADD_IO_SEG(0x00011800E0000490ull) 165 #define CVMX_AGL_GMX_TX_LFSR \ 166 CVMX_ADD_IO_SEG(0x00011800E00004F8ull) 167 #define CVMX_AGL_GMX_TX_OVR_BP \ 168 CVMX_ADD_IO_SEG(0x00011800E00004C8ull) 169 #define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \ 170 CVMX_ADD_IO_SEG(0x00011800E00004A0ull) 171 #define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \ 172 CVMX_ADD_IO_SEG(0x00011800E00004A8ull) 173 174 union cvmx_agl_gmx_bad_reg { 175 uint64_t u64; 176 struct cvmx_agl_gmx_bad_reg_s { 177 uint64_t reserved_38_63:26; 178 uint64_t txpsh1:1; 179 uint64_t txpop1:1; 180 uint64_t ovrflw1:1; 181 uint64_t txpsh:1; 182 uint64_t txpop:1; 183 uint64_t ovrflw:1; 184 uint64_t reserved_27_31:5; 185 uint64_t statovr:1; 186 uint64_t reserved_23_25:3; 187 uint64_t loststat:1; 188 uint64_t reserved_4_21:18; 189 uint64_t out_ovr:2; 190 uint64_t reserved_0_1:2; 191 } s; 192 struct cvmx_agl_gmx_bad_reg_s cn52xx; 193 struct cvmx_agl_gmx_bad_reg_s cn52xxp1; 194 struct cvmx_agl_gmx_bad_reg_cn56xx { 195 uint64_t reserved_35_63:29; 196 uint64_t txpsh:1; 197 uint64_t txpop:1; 198 uint64_t ovrflw:1; 199 uint64_t reserved_27_31:5; 200 uint64_t statovr:1; 201 uint64_t reserved_23_25:3; 202 uint64_t loststat:1; 203 uint64_t reserved_3_21:19; 204 uint64_t out_ovr:1; 205 uint64_t reserved_0_1:2; 206 } cn56xx; 207 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; 208 }; 209 210 union cvmx_agl_gmx_bist { 211 uint64_t u64; 212 struct cvmx_agl_gmx_bist_s { 213 uint64_t reserved_10_63:54; 214 uint64_t status:10; 215 } s; 216 struct cvmx_agl_gmx_bist_s cn52xx; 217 struct cvmx_agl_gmx_bist_s cn52xxp1; 218 struct cvmx_agl_gmx_bist_s cn56xx; 219 struct cvmx_agl_gmx_bist_s cn56xxp1; 220 }; 221 222 union cvmx_agl_gmx_drv_ctl { 223 uint64_t u64; 224 struct cvmx_agl_gmx_drv_ctl_s { 225 uint64_t reserved_49_63:15; 226 uint64_t byp_en1:1; 227 uint64_t reserved_45_47:3; 228 uint64_t pctl1:5; 229 uint64_t reserved_37_39:3; 230 uint64_t nctl1:5; 231 uint64_t reserved_17_31:15; 232 uint64_t byp_en:1; 233 uint64_t reserved_13_15:3; 234 uint64_t pctl:5; 235 uint64_t reserved_5_7:3; 236 uint64_t nctl:5; 237 } s; 238 struct cvmx_agl_gmx_drv_ctl_s cn52xx; 239 struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; 240 struct cvmx_agl_gmx_drv_ctl_cn56xx { 241 uint64_t reserved_17_63:47; 242 uint64_t byp_en:1; 243 uint64_t reserved_13_15:3; 244 uint64_t pctl:5; 245 uint64_t reserved_5_7:3; 246 uint64_t nctl:5; 247 } cn56xx; 248 struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; 249 }; 250 251 union cvmx_agl_gmx_inf_mode { 252 uint64_t u64; 253 struct cvmx_agl_gmx_inf_mode_s { 254 uint64_t reserved_2_63:62; 255 uint64_t en:1; 256 uint64_t reserved_0_0:1; 257 } s; 258 struct cvmx_agl_gmx_inf_mode_s cn52xx; 259 struct cvmx_agl_gmx_inf_mode_s cn52xxp1; 260 struct cvmx_agl_gmx_inf_mode_s cn56xx; 261 struct cvmx_agl_gmx_inf_mode_s cn56xxp1; 262 }; 263 264 union cvmx_agl_gmx_prtx_cfg { 265 uint64_t u64; 266 struct cvmx_agl_gmx_prtx_cfg_s { 267 uint64_t reserved_6_63:58; 268 uint64_t tx_en:1; 269 uint64_t rx_en:1; 270 uint64_t slottime:1; 271 uint64_t duplex:1; 272 uint64_t speed:1; 273 uint64_t en:1; 274 } s; 275 struct cvmx_agl_gmx_prtx_cfg_s cn52xx; 276 struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1; 277 struct cvmx_agl_gmx_prtx_cfg_s cn56xx; 278 struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1; 279 }; 280 281 union cvmx_agl_gmx_rxx_adr_cam0 { 282 uint64_t u64; 283 struct cvmx_agl_gmx_rxx_adr_cam0_s { 284 uint64_t adr:64; 285 } s; 286 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; 287 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; 288 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; 289 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; 290 }; 291 292 union cvmx_agl_gmx_rxx_adr_cam1 { 293 uint64_t u64; 294 struct cvmx_agl_gmx_rxx_adr_cam1_s { 295 uint64_t adr:64; 296 } s; 297 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; 298 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; 299 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; 300 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; 301 }; 302 303 union cvmx_agl_gmx_rxx_adr_cam2 { 304 uint64_t u64; 305 struct cvmx_agl_gmx_rxx_adr_cam2_s { 306 uint64_t adr:64; 307 } s; 308 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; 309 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; 310 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; 311 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; 312 }; 313 314 union cvmx_agl_gmx_rxx_adr_cam3 { 315 uint64_t u64; 316 struct cvmx_agl_gmx_rxx_adr_cam3_s { 317 uint64_t adr:64; 318 } s; 319 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; 320 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; 321 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; 322 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; 323 }; 324 325 union cvmx_agl_gmx_rxx_adr_cam4 { 326 uint64_t u64; 327 struct cvmx_agl_gmx_rxx_adr_cam4_s { 328 uint64_t adr:64; 329 } s; 330 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; 331 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; 332 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; 333 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; 334 }; 335 336 union cvmx_agl_gmx_rxx_adr_cam5 { 337 uint64_t u64; 338 struct cvmx_agl_gmx_rxx_adr_cam5_s { 339 uint64_t adr:64; 340 } s; 341 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; 342 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; 343 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; 344 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; 345 }; 346 347 union cvmx_agl_gmx_rxx_adr_cam_en { 348 uint64_t u64; 349 struct cvmx_agl_gmx_rxx_adr_cam_en_s { 350 uint64_t reserved_8_63:56; 351 uint64_t en:8; 352 } s; 353 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; 354 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; 355 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; 356 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; 357 }; 358 359 union cvmx_agl_gmx_rxx_adr_ctl { 360 uint64_t u64; 361 struct cvmx_agl_gmx_rxx_adr_ctl_s { 362 uint64_t reserved_4_63:60; 363 uint64_t cam_mode:1; 364 uint64_t mcst:2; 365 uint64_t bcst:1; 366 } s; 367 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; 368 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; 369 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; 370 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; 371 }; 372 373 union cvmx_agl_gmx_rxx_decision { 374 uint64_t u64; 375 struct cvmx_agl_gmx_rxx_decision_s { 376 uint64_t reserved_5_63:59; 377 uint64_t cnt:5; 378 } s; 379 struct cvmx_agl_gmx_rxx_decision_s cn52xx; 380 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; 381 struct cvmx_agl_gmx_rxx_decision_s cn56xx; 382 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; 383 }; 384 385 union cvmx_agl_gmx_rxx_frm_chk { 386 uint64_t u64; 387 struct cvmx_agl_gmx_rxx_frm_chk_s { 388 uint64_t reserved_9_63:55; 389 uint64_t skperr:1; 390 uint64_t rcverr:1; 391 uint64_t lenerr:1; 392 uint64_t alnerr:1; 393 uint64_t fcserr:1; 394 uint64_t jabber:1; 395 uint64_t maxerr:1; 396 uint64_t reserved_1_1:1; 397 uint64_t minerr:1; 398 } s; 399 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx; 400 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1; 401 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx; 402 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1; 403 }; 404 405 union cvmx_agl_gmx_rxx_frm_ctl { 406 uint64_t u64; 407 struct cvmx_agl_gmx_rxx_frm_ctl_s { 408 uint64_t reserved_10_63:54; 409 uint64_t pre_align:1; 410 uint64_t pad_len:1; 411 uint64_t vlan_len:1; 412 uint64_t pre_free:1; 413 uint64_t ctl_smac:1; 414 uint64_t ctl_mcst:1; 415 uint64_t ctl_bck:1; 416 uint64_t ctl_drp:1; 417 uint64_t pre_strp:1; 418 uint64_t pre_chk:1; 419 } s; 420 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx; 421 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1; 422 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx; 423 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1; 424 }; 425 426 union cvmx_agl_gmx_rxx_frm_max { 427 uint64_t u64; 428 struct cvmx_agl_gmx_rxx_frm_max_s { 429 uint64_t reserved_16_63:48; 430 uint64_t len:16; 431 } s; 432 struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; 433 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; 434 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; 435 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; 436 }; 437 438 union cvmx_agl_gmx_rxx_frm_min { 439 uint64_t u64; 440 struct cvmx_agl_gmx_rxx_frm_min_s { 441 uint64_t reserved_16_63:48; 442 uint64_t len:16; 443 } s; 444 struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; 445 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; 446 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; 447 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; 448 }; 449 450 union cvmx_agl_gmx_rxx_ifg { 451 uint64_t u64; 452 struct cvmx_agl_gmx_rxx_ifg_s { 453 uint64_t reserved_4_63:60; 454 uint64_t ifg:4; 455 } s; 456 struct cvmx_agl_gmx_rxx_ifg_s cn52xx; 457 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; 458 struct cvmx_agl_gmx_rxx_ifg_s cn56xx; 459 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; 460 }; 461 462 union cvmx_agl_gmx_rxx_int_en { 463 uint64_t u64; 464 struct cvmx_agl_gmx_rxx_int_en_s { 465 uint64_t reserved_20_63:44; 466 uint64_t pause_drp:1; 467 uint64_t reserved_16_18:3; 468 uint64_t ifgerr:1; 469 uint64_t coldet:1; 470 uint64_t falerr:1; 471 uint64_t rsverr:1; 472 uint64_t pcterr:1; 473 uint64_t ovrerr:1; 474 uint64_t reserved_9_9:1; 475 uint64_t skperr:1; 476 uint64_t rcverr:1; 477 uint64_t lenerr:1; 478 uint64_t alnerr:1; 479 uint64_t fcserr:1; 480 uint64_t jabber:1; 481 uint64_t maxerr:1; 482 uint64_t reserved_1_1:1; 483 uint64_t minerr:1; 484 } s; 485 struct cvmx_agl_gmx_rxx_int_en_s cn52xx; 486 struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1; 487 struct cvmx_agl_gmx_rxx_int_en_s cn56xx; 488 struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1; 489 }; 490 491 union cvmx_agl_gmx_rxx_int_reg { 492 uint64_t u64; 493 struct cvmx_agl_gmx_rxx_int_reg_s { 494 uint64_t reserved_20_63:44; 495 uint64_t pause_drp:1; 496 uint64_t reserved_16_18:3; 497 uint64_t ifgerr:1; 498 uint64_t coldet:1; 499 uint64_t falerr:1; 500 uint64_t rsverr:1; 501 uint64_t pcterr:1; 502 uint64_t ovrerr:1; 503 uint64_t reserved_9_9:1; 504 uint64_t skperr:1; 505 uint64_t rcverr:1; 506 uint64_t lenerr:1; 507 uint64_t alnerr:1; 508 uint64_t fcserr:1; 509 uint64_t jabber:1; 510 uint64_t maxerr:1; 511 uint64_t reserved_1_1:1; 512 uint64_t minerr:1; 513 } s; 514 struct cvmx_agl_gmx_rxx_int_reg_s cn52xx; 515 struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1; 516 struct cvmx_agl_gmx_rxx_int_reg_s cn56xx; 517 struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1; 518 }; 519 520 union cvmx_agl_gmx_rxx_jabber { 521 uint64_t u64; 522 struct cvmx_agl_gmx_rxx_jabber_s { 523 uint64_t reserved_16_63:48; 524 uint64_t cnt:16; 525 } s; 526 struct cvmx_agl_gmx_rxx_jabber_s cn52xx; 527 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; 528 struct cvmx_agl_gmx_rxx_jabber_s cn56xx; 529 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; 530 }; 531 532 union cvmx_agl_gmx_rxx_pause_drop_time { 533 uint64_t u64; 534 struct cvmx_agl_gmx_rxx_pause_drop_time_s { 535 uint64_t reserved_16_63:48; 536 uint64_t status:16; 537 } s; 538 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; 539 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; 540 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; 541 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; 542 }; 543 544 union cvmx_agl_gmx_rxx_stats_ctl { 545 uint64_t u64; 546 struct cvmx_agl_gmx_rxx_stats_ctl_s { 547 uint64_t reserved_1_63:63; 548 uint64_t rd_clr:1; 549 } s; 550 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; 551 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; 552 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; 553 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; 554 }; 555 556 union cvmx_agl_gmx_rxx_stats_octs { 557 uint64_t u64; 558 struct cvmx_agl_gmx_rxx_stats_octs_s { 559 uint64_t reserved_48_63:16; 560 uint64_t cnt:48; 561 } s; 562 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; 563 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; 564 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; 565 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; 566 }; 567 568 union cvmx_agl_gmx_rxx_stats_octs_ctl { 569 uint64_t u64; 570 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { 571 uint64_t reserved_48_63:16; 572 uint64_t cnt:48; 573 } s; 574 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; 575 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; 576 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; 577 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; 578 }; 579 580 union cvmx_agl_gmx_rxx_stats_octs_dmac { 581 uint64_t u64; 582 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { 583 uint64_t reserved_48_63:16; 584 uint64_t cnt:48; 585 } s; 586 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; 587 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; 588 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; 589 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; 590 }; 591 592 union cvmx_agl_gmx_rxx_stats_octs_drp { 593 uint64_t u64; 594 struct cvmx_agl_gmx_rxx_stats_octs_drp_s { 595 uint64_t reserved_48_63:16; 596 uint64_t cnt:48; 597 } s; 598 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; 599 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; 600 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; 601 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; 602 }; 603 604 union cvmx_agl_gmx_rxx_stats_pkts { 605 uint64_t u64; 606 struct cvmx_agl_gmx_rxx_stats_pkts_s { 607 uint64_t reserved_32_63:32; 608 uint64_t cnt:32; 609 } s; 610 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; 611 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; 612 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; 613 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; 614 }; 615 616 union cvmx_agl_gmx_rxx_stats_pkts_bad { 617 uint64_t u64; 618 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { 619 uint64_t reserved_32_63:32; 620 uint64_t cnt:32; 621 } s; 622 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; 623 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; 624 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; 625 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; 626 }; 627 628 union cvmx_agl_gmx_rxx_stats_pkts_ctl { 629 uint64_t u64; 630 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { 631 uint64_t reserved_32_63:32; 632 uint64_t cnt:32; 633 } s; 634 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; 635 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; 636 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; 637 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; 638 }; 639 640 union cvmx_agl_gmx_rxx_stats_pkts_dmac { 641 uint64_t u64; 642 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { 643 uint64_t reserved_32_63:32; 644 uint64_t cnt:32; 645 } s; 646 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; 647 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; 648 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; 649 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; 650 }; 651 652 union cvmx_agl_gmx_rxx_stats_pkts_drp { 653 uint64_t u64; 654 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { 655 uint64_t reserved_32_63:32; 656 uint64_t cnt:32; 657 } s; 658 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; 659 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; 660 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; 661 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; 662 }; 663 664 union cvmx_agl_gmx_rxx_udd_skp { 665 uint64_t u64; 666 struct cvmx_agl_gmx_rxx_udd_skp_s { 667 uint64_t reserved_9_63:55; 668 uint64_t fcssel:1; 669 uint64_t reserved_7_7:1; 670 uint64_t len:7; 671 } s; 672 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; 673 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; 674 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; 675 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; 676 }; 677 678 union cvmx_agl_gmx_rx_bp_dropx { 679 uint64_t u64; 680 struct cvmx_agl_gmx_rx_bp_dropx_s { 681 uint64_t reserved_6_63:58; 682 uint64_t mark:6; 683 } s; 684 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; 685 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; 686 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; 687 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; 688 }; 689 690 union cvmx_agl_gmx_rx_bp_offx { 691 uint64_t u64; 692 struct cvmx_agl_gmx_rx_bp_offx_s { 693 uint64_t reserved_6_63:58; 694 uint64_t mark:6; 695 } s; 696 struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; 697 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; 698 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; 699 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; 700 }; 701 702 union cvmx_agl_gmx_rx_bp_onx { 703 uint64_t u64; 704 struct cvmx_agl_gmx_rx_bp_onx_s { 705 uint64_t reserved_9_63:55; 706 uint64_t mark:9; 707 } s; 708 struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; 709 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; 710 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; 711 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; 712 }; 713 714 union cvmx_agl_gmx_rx_prt_info { 715 uint64_t u64; 716 struct cvmx_agl_gmx_rx_prt_info_s { 717 uint64_t reserved_18_63:46; 718 uint64_t drop:2; 719 uint64_t reserved_2_15:14; 720 uint64_t commit:2; 721 } s; 722 struct cvmx_agl_gmx_rx_prt_info_s cn52xx; 723 struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; 724 struct cvmx_agl_gmx_rx_prt_info_cn56xx { 725 uint64_t reserved_17_63:47; 726 uint64_t drop:1; 727 uint64_t reserved_1_15:15; 728 uint64_t commit:1; 729 } cn56xx; 730 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; 731 }; 732 733 union cvmx_agl_gmx_rx_tx_status { 734 uint64_t u64; 735 struct cvmx_agl_gmx_rx_tx_status_s { 736 uint64_t reserved_6_63:58; 737 uint64_t tx:2; 738 uint64_t reserved_2_3:2; 739 uint64_t rx:2; 740 } s; 741 struct cvmx_agl_gmx_rx_tx_status_s cn52xx; 742 struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; 743 struct cvmx_agl_gmx_rx_tx_status_cn56xx { 744 uint64_t reserved_5_63:59; 745 uint64_t tx:1; 746 uint64_t reserved_1_3:3; 747 uint64_t rx:1; 748 } cn56xx; 749 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; 750 }; 751 752 union cvmx_agl_gmx_smacx { 753 uint64_t u64; 754 struct cvmx_agl_gmx_smacx_s { 755 uint64_t reserved_48_63:16; 756 uint64_t smac:48; 757 } s; 758 struct cvmx_agl_gmx_smacx_s cn52xx; 759 struct cvmx_agl_gmx_smacx_s cn52xxp1; 760 struct cvmx_agl_gmx_smacx_s cn56xx; 761 struct cvmx_agl_gmx_smacx_s cn56xxp1; 762 }; 763 764 union cvmx_agl_gmx_stat_bp { 765 uint64_t u64; 766 struct cvmx_agl_gmx_stat_bp_s { 767 uint64_t reserved_17_63:47; 768 uint64_t bp:1; 769 uint64_t cnt:16; 770 } s; 771 struct cvmx_agl_gmx_stat_bp_s cn52xx; 772 struct cvmx_agl_gmx_stat_bp_s cn52xxp1; 773 struct cvmx_agl_gmx_stat_bp_s cn56xx; 774 struct cvmx_agl_gmx_stat_bp_s cn56xxp1; 775 }; 776 777 union cvmx_agl_gmx_txx_append { 778 uint64_t u64; 779 struct cvmx_agl_gmx_txx_append_s { 780 uint64_t reserved_4_63:60; 781 uint64_t force_fcs:1; 782 uint64_t fcs:1; 783 uint64_t pad:1; 784 uint64_t preamble:1; 785 } s; 786 struct cvmx_agl_gmx_txx_append_s cn52xx; 787 struct cvmx_agl_gmx_txx_append_s cn52xxp1; 788 struct cvmx_agl_gmx_txx_append_s cn56xx; 789 struct cvmx_agl_gmx_txx_append_s cn56xxp1; 790 }; 791 792 union cvmx_agl_gmx_txx_ctl { 793 uint64_t u64; 794 struct cvmx_agl_gmx_txx_ctl_s { 795 uint64_t reserved_2_63:62; 796 uint64_t xsdef_en:1; 797 uint64_t xscol_en:1; 798 } s; 799 struct cvmx_agl_gmx_txx_ctl_s cn52xx; 800 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; 801 struct cvmx_agl_gmx_txx_ctl_s cn56xx; 802 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; 803 }; 804 805 union cvmx_agl_gmx_txx_min_pkt { 806 uint64_t u64; 807 struct cvmx_agl_gmx_txx_min_pkt_s { 808 uint64_t reserved_8_63:56; 809 uint64_t min_size:8; 810 } s; 811 struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; 812 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; 813 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; 814 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; 815 }; 816 817 union cvmx_agl_gmx_txx_pause_pkt_interval { 818 uint64_t u64; 819 struct cvmx_agl_gmx_txx_pause_pkt_interval_s { 820 uint64_t reserved_16_63:48; 821 uint64_t interval:16; 822 } s; 823 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; 824 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; 825 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; 826 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; 827 }; 828 829 union cvmx_agl_gmx_txx_pause_pkt_time { 830 uint64_t u64; 831 struct cvmx_agl_gmx_txx_pause_pkt_time_s { 832 uint64_t reserved_16_63:48; 833 uint64_t time:16; 834 } s; 835 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; 836 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; 837 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; 838 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; 839 }; 840 841 union cvmx_agl_gmx_txx_pause_togo { 842 uint64_t u64; 843 struct cvmx_agl_gmx_txx_pause_togo_s { 844 uint64_t reserved_16_63:48; 845 uint64_t time:16; 846 } s; 847 struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; 848 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; 849 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; 850 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; 851 }; 852 853 union cvmx_agl_gmx_txx_pause_zero { 854 uint64_t u64; 855 struct cvmx_agl_gmx_txx_pause_zero_s { 856 uint64_t reserved_1_63:63; 857 uint64_t send:1; 858 } s; 859 struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; 860 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; 861 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; 862 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; 863 }; 864 865 union cvmx_agl_gmx_txx_soft_pause { 866 uint64_t u64; 867 struct cvmx_agl_gmx_txx_soft_pause_s { 868 uint64_t reserved_16_63:48; 869 uint64_t time:16; 870 } s; 871 struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; 872 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; 873 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; 874 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; 875 }; 876 877 union cvmx_agl_gmx_txx_stat0 { 878 uint64_t u64; 879 struct cvmx_agl_gmx_txx_stat0_s { 880 uint64_t xsdef:32; 881 uint64_t xscol:32; 882 } s; 883 struct cvmx_agl_gmx_txx_stat0_s cn52xx; 884 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; 885 struct cvmx_agl_gmx_txx_stat0_s cn56xx; 886 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; 887 }; 888 889 union cvmx_agl_gmx_txx_stat1 { 890 uint64_t u64; 891 struct cvmx_agl_gmx_txx_stat1_s { 892 uint64_t scol:32; 893 uint64_t mcol:32; 894 } s; 895 struct cvmx_agl_gmx_txx_stat1_s cn52xx; 896 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; 897 struct cvmx_agl_gmx_txx_stat1_s cn56xx; 898 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; 899 }; 900 901 union cvmx_agl_gmx_txx_stat2 { 902 uint64_t u64; 903 struct cvmx_agl_gmx_txx_stat2_s { 904 uint64_t reserved_48_63:16; 905 uint64_t octs:48; 906 } s; 907 struct cvmx_agl_gmx_txx_stat2_s cn52xx; 908 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; 909 struct cvmx_agl_gmx_txx_stat2_s cn56xx; 910 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; 911 }; 912 913 union cvmx_agl_gmx_txx_stat3 { 914 uint64_t u64; 915 struct cvmx_agl_gmx_txx_stat3_s { 916 uint64_t reserved_32_63:32; 917 uint64_t pkts:32; 918 } s; 919 struct cvmx_agl_gmx_txx_stat3_s cn52xx; 920 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; 921 struct cvmx_agl_gmx_txx_stat3_s cn56xx; 922 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; 923 }; 924 925 union cvmx_agl_gmx_txx_stat4 { 926 uint64_t u64; 927 struct cvmx_agl_gmx_txx_stat4_s { 928 uint64_t hist1:32; 929 uint64_t hist0:32; 930 } s; 931 struct cvmx_agl_gmx_txx_stat4_s cn52xx; 932 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; 933 struct cvmx_agl_gmx_txx_stat4_s cn56xx; 934 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; 935 }; 936 937 union cvmx_agl_gmx_txx_stat5 { 938 uint64_t u64; 939 struct cvmx_agl_gmx_txx_stat5_s { 940 uint64_t hist3:32; 941 uint64_t hist2:32; 942 } s; 943 struct cvmx_agl_gmx_txx_stat5_s cn52xx; 944 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; 945 struct cvmx_agl_gmx_txx_stat5_s cn56xx; 946 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; 947 }; 948 949 union cvmx_agl_gmx_txx_stat6 { 950 uint64_t u64; 951 struct cvmx_agl_gmx_txx_stat6_s { 952 uint64_t hist5:32; 953 uint64_t hist4:32; 954 } s; 955 struct cvmx_agl_gmx_txx_stat6_s cn52xx; 956 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; 957 struct cvmx_agl_gmx_txx_stat6_s cn56xx; 958 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; 959 }; 960 961 union cvmx_agl_gmx_txx_stat7 { 962 uint64_t u64; 963 struct cvmx_agl_gmx_txx_stat7_s { 964 uint64_t hist7:32; 965 uint64_t hist6:32; 966 } s; 967 struct cvmx_agl_gmx_txx_stat7_s cn52xx; 968 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; 969 struct cvmx_agl_gmx_txx_stat7_s cn56xx; 970 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; 971 }; 972 973 union cvmx_agl_gmx_txx_stat8 { 974 uint64_t u64; 975 struct cvmx_agl_gmx_txx_stat8_s { 976 uint64_t mcst:32; 977 uint64_t bcst:32; 978 } s; 979 struct cvmx_agl_gmx_txx_stat8_s cn52xx; 980 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; 981 struct cvmx_agl_gmx_txx_stat8_s cn56xx; 982 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; 983 }; 984 985 union cvmx_agl_gmx_txx_stat9 { 986 uint64_t u64; 987 struct cvmx_agl_gmx_txx_stat9_s { 988 uint64_t undflw:32; 989 uint64_t ctl:32; 990 } s; 991 struct cvmx_agl_gmx_txx_stat9_s cn52xx; 992 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; 993 struct cvmx_agl_gmx_txx_stat9_s cn56xx; 994 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; 995 }; 996 997 union cvmx_agl_gmx_txx_stats_ctl { 998 uint64_t u64; 999 struct cvmx_agl_gmx_txx_stats_ctl_s { 1000 uint64_t reserved_1_63:63; 1001 uint64_t rd_clr:1; 1002 } s; 1003 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; 1004 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; 1005 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; 1006 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; 1007 }; 1008 1009 union cvmx_agl_gmx_txx_thresh { 1010 uint64_t u64; 1011 struct cvmx_agl_gmx_txx_thresh_s { 1012 uint64_t reserved_6_63:58; 1013 uint64_t cnt:6; 1014 } s; 1015 struct cvmx_agl_gmx_txx_thresh_s cn52xx; 1016 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; 1017 struct cvmx_agl_gmx_txx_thresh_s cn56xx; 1018 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; 1019 }; 1020 1021 union cvmx_agl_gmx_tx_bp { 1022 uint64_t u64; 1023 struct cvmx_agl_gmx_tx_bp_s { 1024 uint64_t reserved_2_63:62; 1025 uint64_t bp:2; 1026 } s; 1027 struct cvmx_agl_gmx_tx_bp_s cn52xx; 1028 struct cvmx_agl_gmx_tx_bp_s cn52xxp1; 1029 struct cvmx_agl_gmx_tx_bp_cn56xx { 1030 uint64_t reserved_1_63:63; 1031 uint64_t bp:1; 1032 } cn56xx; 1033 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; 1034 }; 1035 1036 union cvmx_agl_gmx_tx_col_attempt { 1037 uint64_t u64; 1038 struct cvmx_agl_gmx_tx_col_attempt_s { 1039 uint64_t reserved_5_63:59; 1040 uint64_t limit:5; 1041 } s; 1042 struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; 1043 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; 1044 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; 1045 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; 1046 }; 1047 1048 union cvmx_agl_gmx_tx_ifg { 1049 uint64_t u64; 1050 struct cvmx_agl_gmx_tx_ifg_s { 1051 uint64_t reserved_8_63:56; 1052 uint64_t ifg2:4; 1053 uint64_t ifg1:4; 1054 } s; 1055 struct cvmx_agl_gmx_tx_ifg_s cn52xx; 1056 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; 1057 struct cvmx_agl_gmx_tx_ifg_s cn56xx; 1058 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; 1059 }; 1060 1061 union cvmx_agl_gmx_tx_int_en { 1062 uint64_t u64; 1063 struct cvmx_agl_gmx_tx_int_en_s { 1064 uint64_t reserved_18_63:46; 1065 uint64_t late_col:2; 1066 uint64_t reserved_14_15:2; 1067 uint64_t xsdef:2; 1068 uint64_t reserved_10_11:2; 1069 uint64_t xscol:2; 1070 uint64_t reserved_4_7:4; 1071 uint64_t undflw:2; 1072 uint64_t reserved_1_1:1; 1073 uint64_t pko_nxa:1; 1074 } s; 1075 struct cvmx_agl_gmx_tx_int_en_s cn52xx; 1076 struct cvmx_agl_gmx_tx_int_en_s cn52xxp1; 1077 struct cvmx_agl_gmx_tx_int_en_cn56xx { 1078 uint64_t reserved_17_63:47; 1079 uint64_t late_col:1; 1080 uint64_t reserved_13_15:3; 1081 uint64_t xsdef:1; 1082 uint64_t reserved_9_11:3; 1083 uint64_t xscol:1; 1084 uint64_t reserved_3_7:5; 1085 uint64_t undflw:1; 1086 uint64_t reserved_1_1:1; 1087 uint64_t pko_nxa:1; 1088 } cn56xx; 1089 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; 1090 }; 1091 1092 union cvmx_agl_gmx_tx_int_reg { 1093 uint64_t u64; 1094 struct cvmx_agl_gmx_tx_int_reg_s { 1095 uint64_t reserved_18_63:46; 1096 uint64_t late_col:2; 1097 uint64_t reserved_14_15:2; 1098 uint64_t xsdef:2; 1099 uint64_t reserved_10_11:2; 1100 uint64_t xscol:2; 1101 uint64_t reserved_4_7:4; 1102 uint64_t undflw:2; 1103 uint64_t reserved_1_1:1; 1104 uint64_t pko_nxa:1; 1105 } s; 1106 struct cvmx_agl_gmx_tx_int_reg_s cn52xx; 1107 struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1; 1108 struct cvmx_agl_gmx_tx_int_reg_cn56xx { 1109 uint64_t reserved_17_63:47; 1110 uint64_t late_col:1; 1111 uint64_t reserved_13_15:3; 1112 uint64_t xsdef:1; 1113 uint64_t reserved_9_11:3; 1114 uint64_t xscol:1; 1115 uint64_t reserved_3_7:5; 1116 uint64_t undflw:1; 1117 uint64_t reserved_1_1:1; 1118 uint64_t pko_nxa:1; 1119 } cn56xx; 1120 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; 1121 }; 1122 1123 union cvmx_agl_gmx_tx_jam { 1124 uint64_t u64; 1125 struct cvmx_agl_gmx_tx_jam_s { 1126 uint64_t reserved_8_63:56; 1127 uint64_t jam:8; 1128 } s; 1129 struct cvmx_agl_gmx_tx_jam_s cn52xx; 1130 struct cvmx_agl_gmx_tx_jam_s cn52xxp1; 1131 struct cvmx_agl_gmx_tx_jam_s cn56xx; 1132 struct cvmx_agl_gmx_tx_jam_s cn56xxp1; 1133 }; 1134 1135 union cvmx_agl_gmx_tx_lfsr { 1136 uint64_t u64; 1137 struct cvmx_agl_gmx_tx_lfsr_s { 1138 uint64_t reserved_16_63:48; 1139 uint64_t lfsr:16; 1140 } s; 1141 struct cvmx_agl_gmx_tx_lfsr_s cn52xx; 1142 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; 1143 struct cvmx_agl_gmx_tx_lfsr_s cn56xx; 1144 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; 1145 }; 1146 1147 union cvmx_agl_gmx_tx_ovr_bp { 1148 uint64_t u64; 1149 struct cvmx_agl_gmx_tx_ovr_bp_s { 1150 uint64_t reserved_10_63:54; 1151 uint64_t en:2; 1152 uint64_t reserved_6_7:2; 1153 uint64_t bp:2; 1154 uint64_t reserved_2_3:2; 1155 uint64_t ign_full:2; 1156 } s; 1157 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; 1158 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; 1159 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { 1160 uint64_t reserved_9_63:55; 1161 uint64_t en:1; 1162 uint64_t reserved_5_7:3; 1163 uint64_t bp:1; 1164 uint64_t reserved_1_3:3; 1165 uint64_t ign_full:1; 1166 } cn56xx; 1167 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; 1168 }; 1169 1170 union cvmx_agl_gmx_tx_pause_pkt_dmac { 1171 uint64_t u64; 1172 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { 1173 uint64_t reserved_48_63:16; 1174 uint64_t dmac:48; 1175 } s; 1176 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; 1177 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; 1178 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; 1179 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; 1180 }; 1181 1182 union cvmx_agl_gmx_tx_pause_pkt_type { 1183 uint64_t u64; 1184 struct cvmx_agl_gmx_tx_pause_pkt_type_s { 1185 uint64_t reserved_16_63:48; 1186 uint64_t type:16; 1187 } s; 1188 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; 1189 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; 1190 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; 1191 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; 1192 }; 1193 1194 #endif 
new file arch/mips/include/asm/octeon/cvmxmixxdefs.h
 + 1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 20032008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * ASIS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 021101301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_MIXX_DEFS_H__ 29 #define __CVMX_MIXX_DEFS_H__ 30 31 #define CVMX_MIXX_BIST(offset) \ 32 CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048)) 33 #define CVMX_MIXX_CTL(offset) \ 34 CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048)) 35 #define CVMX_MIXX_INTENA(offset) \ 36 CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048)) 37 #define CVMX_MIXX_IRCNT(offset) \ 38 CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048)) 39 #define CVMX_MIXX_IRHWM(offset) \ 40 CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048)) 41 #define CVMX_MIXX_IRING1(offset) \ 42 CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048)) 43 #define CVMX_MIXX_IRING2(offset) \ 44 CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048)) 45 #define CVMX_MIXX_ISR(offset) \ 46 CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048)) 47 #define CVMX_MIXX_ORCNT(offset) \ 48 CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048)) 49 #define CVMX_MIXX_ORHWM(offset) \ 50 CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048)) 51 #define CVMX_MIXX_ORING1(offset) \ 52 CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048)) 53 #define CVMX_MIXX_ORING2(offset) \ 54 CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048)) 55 #define CVMX_MIXX_REMCNT(offset) \ 56 CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048)) 57 58 union cvmx_mixx_bist { 59 uint64_t u64; 60 struct cvmx_mixx_bist_s { 61 uint64_t reserved_4_63:60; 62 uint64_t mrqdat:1; 63 uint64_t ipfdat:1; 64 uint64_t irfdat:1; 65 uint64_t orfdat:1; 66 } s; 67 struct cvmx_mixx_bist_s cn52xx; 68 struct cvmx_mixx_bist_s cn52xxp1; 69 struct cvmx_mixx_bist_s cn56xx; 70 struct cvmx_mixx_bist_s cn56xxp1; 71 }; 72 73 union cvmx_mixx_ctl { 74 uint64_t u64; 75 struct cvmx_mixx_ctl_s { 76 uint64_t reserved_8_63:56; 77 uint64_t crc_strip:1; 78 uint64_t busy:1; 79 uint64_t en:1; 80 uint64_t reset:1; 81 uint64_t lendian:1; 82 uint64_t nbtarb:1; 83 uint64_t mrq_hwm:2; 84 } s; 85 struct cvmx_mixx_ctl_s cn52xx; 86 struct cvmx_mixx_ctl_s cn52xxp1; 87 struct cvmx_mixx_ctl_s cn56xx; 88 struct cvmx_mixx_ctl_s cn56xxp1; 89 }; 90 91 union cvmx_mixx_intena { 92 uint64_t u64; 93 struct cvmx_mixx_intena_s { 94 uint64_t reserved_7_63:57; 95 uint64_t orunena:1; 96 uint64_t irunena:1; 97 uint64_t data_drpena:1; 98 uint64_t ithena:1; 99 uint64_t othena:1; 100 uint64_t ivfena:1; 101 uint64_t ovfena:1; 102 } s; 103 struct cvmx_mixx_intena_s cn52xx; 104 struct cvmx_mixx_intena_s cn52xxp1; 105 struct cvmx_mixx_intena_s cn56xx; 106 struct cvmx_mixx_intena_s cn56xxp1; 107 }; 108 109 union cvmx_mixx_ircnt { 110 uint64_t u64; 111 struct cvmx_mixx_ircnt_s { 112 uint64_t reserved_20_63:44; 113 uint64_t ircnt:20; 114 } s; 115 struct cvmx_mixx_ircnt_s cn52xx; 116 struct cvmx_mixx_ircnt_s cn52xxp1; 117 struct cvmx_mixx_ircnt_s cn56xx; 118 struct cvmx_mixx_ircnt_s cn56xxp1; 119 }; 120 121 union cvmx_mixx_irhwm { 122 uint64_t u64; 123 struct cvmx_mixx_irhwm_s { 124 uint64_t reserved_40_63:24; 125 uint64_t ibplwm:20; 126 uint64_t irhwm:20; 127 } s; 128 struct cvmx_mixx_irhwm_s cn52xx; 129 struct cvmx_mixx_irhwm_s cn52xxp1; 130 struct cvmx_mixx_irhwm_s cn56xx; 131 struct cvmx_mixx_irhwm_s cn56xxp1; 132 }; 133 134 union cvmx_mixx_iring1 { 135 uint64_t u64; 136 struct cvmx_mixx_iring1_s { 137 uint64_t reserved_60_63:4; 138 uint64_t isize:20; 139 uint64_t reserved_36_39:4; 140 uint64_t ibase:33; 141 uint64_t reserved_0_2:3; 142 } s; 143 struct cvmx_mixx_iring1_s cn52xx; 144 struct cvmx_mixx_iring1_s cn52xxp1; 145 struct cvmx_mixx_iring1_s cn56xx; 146 struct cvmx_mixx_iring1_s cn56xxp1; 147 }; 148 149 union cvmx_mixx_iring2 { 150 uint64_t u64; 151 struct cvmx_mixx_iring2_s { 152 uint64_t reserved_52_63:12; 153 uint64_t itlptr:20; 154 uint64_t reserved_20_31:12; 155 uint64_t idbell:20; 156 } s; 157 struct cvmx_mixx_iring2_s cn52xx; 158 struct cvmx_mixx_iring2_s cn52xxp1; 159 struct cvmx_mixx_iring2_s cn56xx; 160 struct cvmx_mixx_iring2_s cn56xxp1; 161 }; 162 163 union cvmx_mixx_isr { 164 uint64_t u64; 165 struct cvmx_mixx_isr_s { 166 uint64_t reserved_7_63:57; 167 uint64_t orun:1; 168 uint64_t irun:1; 169 uint64_t data_drp:1; 170 uint64_t irthresh:1; 171 uint64_t orthresh:1; 172 uint64_t idblovf:1; 173 uint64_t odblovf:1; 174 } s; 175 struct cvmx_mixx_isr_s cn52xx; 176 struct cvmx_mixx_isr_s cn52xxp1; 177 struct cvmx_mixx_isr_s cn56xx; 178 struct cvmx_mixx_isr_s cn56xxp1; 179 }; 180 181 union cvmx_mixx_orcnt { 182 uint64_t u64; 183 struct cvmx_mixx_orcnt_s { 184 uint64_t reserved_20_63:44; 185 uint64_t orcnt:20; 186 } s; 187 struct cvmx_mixx_orcnt_s cn52xx; 188 struct cvmx_mixx_orcnt_s cn52xxp1; 189 struct cvmx_mixx_orcnt_s cn56xx; 190 struct cvmx_mixx_orcnt_s cn56xxp1; 191 }; 192 193 union cvmx_mixx_orhwm { 194 uint64_t u64; 195 struct cvmx_mixx_orhwm_s { 196 uint64_t reserved_20_63:44; 197 uint64_t orhwm:20; 198 } s; 199 struct cvmx_mixx_orhwm_s cn52xx; 200 struct cvmx_mixx_orhwm_s cn52xxp1; 201 struct cvmx_mixx_orhwm_s cn56xx; 202 struct cvmx_mixx_orhwm_s cn56xxp1; 203 }; 204 205 union cvmx_mixx_oring1 { 206 uint64_t u64; 207 struct cvmx_mixx_oring1_s { 208 uint64_t reserved_60_63:4; 209 uint64_t osize:20; 210 uint64_t reserved_36_39:4; 211 uint64_t obase:33; 212 uint64_t reserved_0_2:3; 213 } s; 214 struct cvmx_mixx_oring1_s cn52xx; 215 struct cvmx_mixx_oring1_s cn52xxp1; 216 struct cvmx_mixx_oring1_s cn56xx; 217 struct cvmx_mixx_oring1_s cn56xxp1; 218 }; 219 220 union cvmx_mixx_oring2 { 221 uint64_t u64; 222 struct cvmx_mixx_oring2_s { 223 uint64_t reserved_52_63:12; 224 uint64_t otlptr:20; 225 uint64_t reserved_20_31:12; 226 uint64_t odbell:20; 227 } s; 228 struct cvmx_mixx_oring2_s cn52xx; 229 struct cvmx_mixx_oring2_s cn52xxp1; 230 struct cvmx_mixx_oring2_s cn56xx; 231 struct cvmx_mixx_oring2_s cn56xxp1; 232 }; 233 234 union cvmx_mixx_remcnt { 235 uint64_t u64; 236 struct cvmx_mixx_remcnt_s { 237 uint64_t reserved_52_63:12; 238 uint64_t iremcnt:20; 239 uint64_t reserved_20_31:12; 240 uint64_t oremcnt:20; 241 } s; 242 struct cvmx_mixx_remcnt_s cn52xx; 243 struct cvmx_mixx_remcnt_s cn52xxp1; 244 struct cvmx_mixx_remcnt_s cn56xx; 245 struct cvmx_mixx_remcnt_s cn56xxp1; 246 }; 247 248 #endif 
new file arch/mips/include/asm/octeon/cvmxsmixdefs.h
 + 1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 20032008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * ASIS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 021101301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_SMIX_DEFS_H__ 29 #define __CVMX_SMIX_DEFS_H__ 30 31 #define CVMX_SMIX_CLK(offset) \ 32 CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) 33 #define CVMX_SMIX_CMD(offset) \ 34 CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) 35 #define CVMX_SMIX_EN(offset) \ 36 CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256)) 37 #define CVMX_SMIX_RD_DAT(offset) \ 38 CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256)) 39 #define CVMX_SMIX_WR_DAT(offset) \ 40 CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256)) 41 42 union cvmx_smix_clk { 43 uint64_t u64; 44 struct cvmx_smix_clk_s { 45 uint64_t reserved_25_63:39; 46 uint64_t mode:1; 47 uint64_t reserved_21_23:3; 48 uint64_t sample_hi:5; 49 uint64_t sample_mode:1; 50 uint64_t reserved_14_14:1; 51 uint64_t clk_idle:1; 52 uint64_t preamble:1; 53 uint64_t sample:4; 54 uint64_t phase:8; 55 } s; 56 struct cvmx_smix_clk_cn30xx { 57 uint64_t reserved_21_63:43; 58 uint64_t sample_hi:5; 59 uint64_t reserved_14_15:2; 60 uint64_t clk_idle:1; 61 uint64_t preamble:1; 62 uint64_t sample:4; 63 uint64_t phase:8; 64 } cn30xx; 65 struct cvmx_smix_clk_cn30xx cn31xx; 66 struct cvmx_smix_clk_cn30xx cn38xx; 67 struct cvmx_smix_clk_cn30xx cn38xxp2; 68 struct cvmx_smix_clk_cn50xx { 69 uint64_t reserved_25_63:39; 70 uint64_t mode:1; 71 uint64_t reserved_21_23:3; 72 uint64_t sample_hi:5; 73 uint64_t reserved_14_15:2; 74 uint64_t clk_idle:1; 75 uint64_t preamble:1; 76 uint64_t sample:4; 77 uint64_t phase:8; 78 } cn50xx; 79 struct cvmx_smix_clk_s cn52xx; 80 struct cvmx_smix_clk_cn50xx cn52xxp1; 81 struct cvmx_smix_clk_s cn56xx; 82 struct cvmx_smix_clk_cn50xx cn56xxp1; 83 struct cvmx_smix_clk_cn30xx cn58xx; 84 struct cvmx_smix_clk_cn30xx cn58xxp1; 85 }; 86 87 union cvmx_smix_cmd { 88 uint64_t u64; 89 struct cvmx_smix_cmd_s { 90 uint64_t reserved_18_63:46; 91 uint64_t phy_op:2; 92 uint64_t reserved_13_15:3; 93 uint64_t phy_adr:5; 94 uint64_t reserved_5_7:3; 95 uint64_t reg_adr:5; 96 } s; 97 struct cvmx_smix_cmd_cn30xx { 98 uint64_t reserved_17_63:47; 99 uint64_t phy_op:1; 100 uint64_t reserved_13_15:3; 101 uint64_t phy_adr:5; 102 uint64_t reserved_5_7:3; 103 uint64_t reg_adr:5; 104 } cn30xx; 105 struct cvmx_smix_cmd_cn30xx cn31xx; 106 struct cvmx_smix_cmd_cn30xx cn38xx; 107 struct cvmx_smix_cmd_cn30xx cn38xxp2; 108 struct cvmx_smix_cmd_s cn50xx; 109 struct cvmx_smix_cmd_s cn52xx; 110 struct cvmx_smix_cmd_s cn52xxp1; 111 struct cvmx_smix_cmd_s cn56xx; 112 struct cvmx_smix_cmd_s cn56xxp1; 113 struct cvmx_smix_cmd_cn30xx cn58xx; 114 struct cvmx_smix_cmd_cn30xx cn58xxp1; 115 }; 116 117 union cvmx_smix_en { 118 uint64_t u64; 119 struct cvmx_smix_en_s { 120 uint64_t reserved_1_63:63; 121 uint64_t en:1; 122 } s; 123 struct cvmx_smix_en_s cn30xx; 124 struct cvmx_smix_en_s cn31xx; 125 struct cvmx_smix_en_s cn38xx; 126 struct cvmx_smix_en_s cn38xxp2; 127 struct cvmx_smix_en_s cn50xx; 128 struct cvmx_smix_en_s cn52xx; 129 struct cvmx_smix_en_s cn52xxp1; 130 struct cvmx_smix_en_s cn56xx; 131 struct cvmx_smix_en_s cn56xxp1; 132 struct cvmx_smix_en_s cn58xx; 133 struct cvmx_smix_en_s cn58xxp1; 134 }; 135 136 union cvmx_smix_rd_dat { 137 uint64_t u64; 138 struct cvmx_smix_rd_dat_s { 139 uint64_t reserved_18_63:46; 140 uint64_t pending:1; 141 uint64_t val:1; 142 uint64_t dat:16; 143 } s; 144 struct cvmx_smix_rd_dat_s cn30xx; 145 struct cvmx_smix_rd_dat_s cn31xx; 146 struct cvmx_smix_rd_dat_s cn38xx; 147 struct cvmx_smix_rd_dat_s cn38xxp2; 148 struct cvmx_smix_rd_dat_s cn50xx; 149 struct cvmx_smix_rd_dat_s cn52xx; 150 struct cvmx_smix_rd_dat_s cn52xxp1; 151 struct cvmx_smix_rd_dat_s cn56xx; 152 struct cvmx_smix_rd_dat_s cn56xxp1; 153 struct cvmx_smix_rd_dat_s cn58xx; 154 struct cvmx_smix_rd_dat_s cn58xxp1; 155 }; 156 157 union cvmx_smix_wr_dat { 158 uint64_t u64; 159 struct cvmx_smix_wr_dat_s { 160 uint64_t reserved_18_63:46; 161 uint64_t pending:1; 162 uint64_t val:1; 163 uint64_t dat:16; 164 } s; 165 struct cvmx_smix_wr_dat_s cn30xx; 166 struct cvmx_smix_wr_dat_s cn31xx; 167 struct cvmx_smix_wr_dat_s cn38xx; 168 struct cvmx_smix_wr_dat_s cn38xxp2; 169 struct cvmx_smix_wr_dat_s cn50xx; 170 struct cvmx_smix_wr_dat_s cn52xx; 171 struct cvmx_smix_wr_dat_s cn52xxp1; 172 struct cvmx_smix_wr_dat_s cn56xx; 173 struct cvmx_smix_wr_dat_s cn56xxp1; 174 struct cvmx_smix_wr_dat_s cn58xx; 175 struct cvmx_smix_wr_dat_s cn58xxp1; 176 }; 177 178 #endif
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