source: trunk/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @ 31401

Last change on this file since 31401 was 31401, checked in by juhosg, 5 years ago

ramips: rt305x: fix CPU clock detection on RT3352

File size: 5.2 KB
Line 
1/*
2 *  Ralink RT305 SoC register definitions
3 *
4 *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 *
6 *  This program is free software; you can redistribute it and/or modify it
7 *  under the terms of the GNU General Public License version 2 as published
8 *  by the Free Software Foundation.
9 */
10
11#ifndef _RT305X_REGS_H_
12#define _RT305X_REGS_H_
13
14#include <linux/bitops.h>
15
16#define RT305X_SDRAM_BASE       0x00000000
17#define RT305X_SYSC_BASE        0x10000000
18#define RT305X_TIMER_BASE       0x10000100
19#define RT305X_INTC_BASE        0x10000200
20#define RT305X_MEMC_BASE        0x10000300
21#define RT305X_PCM_BASE         0x10000400
22#define RT305X_UART0_BASE       0x10000500
23#define RT305X_PIO_BASE         0x10000600
24#define RT305X_GDMA_BASE        0x10000700
25#define RT305X_NANDC_BASE       0x10000800
26#define RT305X_I2C_BASE         0x10000900
27#define RT305X_I2S_BASE         0x10000a00
28#define RT305X_SPI_BASE         0x10000b00
29#define RT305X_UART1_BASE       0x10000c00
30#define RT305X_FE_BASE          0x10100000
31#define RT305X_SWITCH_BASE      0x10110000
32#define RT305X_WMAC_BASE        0x10180000
33#define RT305X_OTG_BASE         0x101c0000
34#define RT305X_ROM_BASE         0x00400000
35#define RT305X_FLASH1_BASE      0x1b000000
36#define RT305X_FLASH0_BASE      0x1f000000
37
38#define RT305X_SYSC_SIZE        0x100
39#define RT305X_TIMER_SIZE       0x100
40#define RT305X_INTC_SIZE        0x100
41#define RT305X_MEMC_SIZE        0x100
42#define RT305X_UART0_SIZE       0x100
43#define RT305X_PIO_SIZE         0x100
44#define RT305X_UART1_SIZE       0x100
45#define RT305X_SPI_SIZE         0x100
46#define RT305X_FLASH1_SIZE      (16 * 1024 * 1024)
47#define RT305X_FLASH0_SIZE      (8 * 1024 * 1024)
48
49/* SYSC registers */
50#define SYSC_REG_CHIP_NAME0     0x000   /* Chip Name 0 */
51#define SYSC_REG_CHIP_NAME1     0x004   /* Chip Name 1 */
52#define SYSC_REG_CHIP_ID        0x00c   /* Chip Identification */
53#define SYSC_REG_SYSTEM_CONFIG  0x010   /* System Configuration */
54#define SYSC_REG_RESET_CTRL     0x034   /* Reset Control*/
55#define SYSC_REG_RESET_STATUS   0x038   /* Reset Status*/
56#define SYSC_REG_GPIO_MODE      0x060   /* GPIO Purpose Select */
57#define SYSC_REG_IA_ADDRESS     0x310   /* Illegal Access Address */
58#define SYSC_REG_IA_TYPE        0x314   /* Illegal Access Type */
59
60#define RT3052_CHIP_NAME0       0x30335452
61#define RT3052_CHIP_NAME1       0x20203235
62
63#define RT3350_CHIP_NAME0       0x33335452
64#define RT3350_CHIP_NAME1       0x20203035
65
66#define RT3352_CHIP_NAME0       0x33335452
67#define RT3352_CHIP_NAME1       0x20203235
68
69#define CHIP_ID_ID_MASK         0xff
70#define CHIP_ID_ID_SHIFT        8
71#define CHIP_ID_REV_MASK        0xff
72
73#define RT305X_SYSCFG_CPUCLK_SHIFT      18
74#define RT305X_SYSCFG_CPUCLK_MASK       0x1
75#define RT305X_SYSCFG_CPUCLK_LOW        0x0
76#define RT305X_SYSCFG_CPUCLK_HIGH       0x1
77#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT       2
78#define RT305X_SYSCFG_SRAM_CS0_MODE_MASK        0x3
79#define RT305X_SYSCFG_SRAM_CS0_MODE_NORMAL      0
80#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT         1
81#define RT305X_SYSCFG_SRAM_CS0_MODE_BTCOEX      2
82
83#define RT3352_SYSCFG0_CPUCLK_SHIFT     8
84#define RT3352_SYSCFG0_CPUCLK_MASK      0x1
85#define RT3352_SYSCFG0_CPUCLK_LOW       0x0
86#define RT3352_SYSCFG0_CPUCLK_HIGH      0x1
87
88#define RT305X_GPIO_MODE_I2C            BIT(0)
89#define RT305X_GPIO_MODE_SPI            BIT(1)
90#define RT305X_GPIO_MODE_UART0_SHIFT    2
91#define RT305X_GPIO_MODE_UART0_MASK     0x7
92#define RT305X_GPIO_MODE_UART0(x)       ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
93#define RT305X_GPIO_MODE_UARTF          0x0
94#define RT305X_GPIO_MODE_PCM_UARTF      0x1
95#define RT305X_GPIO_MODE_PCM_I2S        0x2
96#define RT305X_GPIO_MODE_I2S_UARTF      0x3
97#define RT305X_GPIO_MODE_PCM_GPIO       0x4
98#define RT305X_GPIO_MODE_GPIO_UARTF     0x5
99#define RT305X_GPIO_MODE_GPIO_I2S       0x6
100#define RT305X_GPIO_MODE_GPIO           0x7
101#define RT305X_GPIO_MODE_UART1          BIT(5)
102#define RT305X_GPIO_MODE_JTAG           BIT(6)
103#define RT305X_GPIO_MODE_MDIO           BIT(7)
104#define RT305X_GPIO_MODE_SDRAM          BIT(8)
105#define RT305X_GPIO_MODE_RGMII          BIT(9)
106
107#define RT305X_RESET_SYSTEM     BIT(0)
108#define RT305X_RESET_TIMER      BIT(8)
109#define RT305X_RESET_INTC       BIT(9)
110#define RT305X_RESET_MEMC       BIT(10)
111#define RT305X_RESET_PCM        BIT(11)
112#define RT305X_RESET_UART0      BIT(12)
113#define RT305X_RESET_PIO        BIT(13)
114#define RT305X_RESET_DMA        BIT(14)
115#define RT305X_RESET_I2C        BIT(16)
116#define RT305X_RESET_I2S        BIT(17)
117#define RT305X_RESET_SPI        BIT(18)
118#define RT305X_RESET_UART1      BIT(19)
119#define RT305X_RESET_WNIC       BIT(20)
120#define RT305X_RESET_FE         BIT(21)
121#define RT305X_RESET_OTG        BIT(22)
122#define RT305X_RESET_ESW        BIT(23)
123
124#define RT305X_INTC_INT_SYSCTL  BIT(0)
125#define RT305X_INTC_INT_TIMER0  BIT(1)
126#define RT305X_INTC_INT_TIMER1  BIT(2)
127#define RT305X_INTC_INT_IA      BIT(3)
128#define RT305X_INTC_INT_PCM     BIT(4)
129#define RT305X_INTC_INT_UART0   BIT(5)
130#define RT305X_INTC_INT_PIO     BIT(6)
131#define RT305X_INTC_INT_DMA     BIT(7)
132#define RT305X_INTC_INT_NAND    BIT(8)
133#define RT305X_INTC_INT_PERFC   BIT(9)
134#define RT305X_INTC_INT_I2S     BIT(10)
135#define RT305X_INTC_INT_UART1   BIT(12)
136#define RT305X_INTC_INT_ESW     BIT(17)
137#define RT305X_INTC_INT_OTG     BIT(18)
138#define RT305X_INTC_INT_GLOBAL  BIT(31)
139
140/* MEMC registers */
141#define MEMC_REG_SDRAM_CFG0     0x00
142#define MEMC_REG_SDRAM_CFG1     0x04
143#define MEMC_REG_FLASH_CFG0     0x08
144#define MEMC_REG_FLASH_CFG1     0x0c
145#define MEMC_REG_IA_ADDR        0x10
146#define MEMC_REG_IA_TYPE        0x14
147
148#define FLASH_CFG_WIDTH_SHIFT   26
149#define FLASH_CFG_WIDTH_MASK    0x3
150#define FLASH_CFG_WIDTH_8BIT    0x0
151#define FLASH_CFG_WIDTH_16BIT   0x1
152#define FLASH_CFG_WIDTH_32BIT   0x2
153
154/* UART registers */
155#define UART_REG_RX     0
156#define UART_REG_TX     1
157#define UART_REG_IER    2
158#define UART_REG_IIR    3
159#define UART_REG_FCR    4
160#define UART_REG_LCR    5
161#define UART_REG_MCR    6
162#define UART_REG_LSR    7
163
164#endif /* _RT305X_REGS_H_ */
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