source: trunk/target/linux/xburst/patches-3.2/0014-MIPS-JZ4740-reset-Initialize-hibernate-wakeup-counte.patch @ 31222

Last change on this file since 31222 was 31222, checked in by jogo, 5 years ago

kernel: update linux 3.2 to 3.2.14

File size: 2.9 KB
  • arch/mips/jz4740/reset.c

    From 2dcb0ca66d0bffc23d5f001fad81fb1a7a2c371b Mon Sep 17 00:00:00 2001
    From: Maarten ter Huurne <maarten@treewalker.org>
    Date: Tue, 28 Jun 2011 22:28:59 +0200
    Subject: [PATCH 14/21] MIPS: JZ4740: reset: Initialize hibernate wakeup
     counters.
    
    In hibernation mode only the wakeup logic and the RTC are left running,
    so this is what users perceive as power down.
    
    If the counters are not initialized, the corresponding pin (typically
    connected to the power button) has to be asserted for two seconds
    before the device wakes up. Most users expect a shorter wakeup time.
    
    I took the timing values of 100 ms and 60 ms from BouKiCHi's patch for
    the Dingoo A320 kernel.
    ---
     arch/mips/jz4740/reset.c |   46 ++++++++++++++++++++++++++++++++++++++++------
     1 files changed, 40 insertions(+), 6 deletions(-)
    
    a b  
    2121#include <asm/mach-jz4740/base.h> 
    2222#include <asm/mach-jz4740/timer.h> 
    2323 
     24#include "reset.h" 
     25#include "clock.h" 
     26 
    2427static void jz4740_halt(void) 
    2528{ 
    2629        while (1) { 
    static void jz4740_restart(char *command 
    5356        jz4740_halt(); 
    5457} 
    5558 
    56 #define JZ_REG_RTC_CTRL         0x00 
    57 #define JZ_REG_RTC_HIBERNATE    0x20 
    58  
    59 #define JZ_RTC_CTRL_WRDY        BIT(7) 
     59#define JZ_REG_RTC_CTRL                 0x00 
     60#define JZ_REG_RTC_HIBERNATE            0x20 
     61#define JZ_REG_RTC_WAKEUP_FILTER        0x24 
     62#define JZ_REG_RTC_RESET_COUNTER        0x28 
     63 
     64#define JZ_RTC_CTRL_WRDY                BIT(7) 
     65#define JZ_RTC_WAKEUP_FILTER_MASK       0x0000FFE0 
     66#define JZ_RTC_RESET_COUNTER_MASK       0x00000FE0 
    6067 
    61 static void jz4740_power_off(void) 
     68static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base) 
    6269{ 
    63         void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24); 
    6470        uint32_t ctrl; 
    65  
    6671        do { 
    6772                ctrl = readl(rtc_base + JZ_REG_RTC_CTRL); 
    6873        } while (!(ctrl & JZ_RTC_CTRL_WRDY)); 
     74} 
    6975 
     76static void jz4740_power_off(void) 
     77{ 
     78        void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38); 
     79        unsigned long long wakeup_filter_ticks; 
     80        unsigned long long reset_counter_ticks; 
     81 
     82        /* Set minimum wakeup pin assertion time: 100 ms. 
     83           Range is 0 to 2 sec if RTC is clocked at 32 kHz. */ 
     84        wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000; 
     85        if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK) 
     86                wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK; 
     87        else 
     88                wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK; 
     89        jz4740_rtc_wait_ready(rtc_base); 
     90        writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER); 
     91 
     92        /* Set reset pin low-level assertion time after wakeup: 60 ms. 
     93           Range is 0 to 125 ms if RTC is clocked at 32 kHz. */ 
     94        reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000; 
     95        if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK) 
     96                reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK; 
     97        else 
     98                reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK; 
     99        jz4740_rtc_wait_ready(rtc_base); 
     100        writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER); 
     101 
     102        jz4740_rtc_wait_ready(rtc_base); 
    70103        writel(1, rtc_base + JZ_REG_RTC_HIBERNATE); 
     104 
    71105        jz4740_halt(); 
    72106} 
    73107 
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