source: trunk/toolchain/gcc/patches/linaro/995-fa526.patch @ 27118

Last change on this file since 27118 was 27118, checked in by mirko, 5 years ago

[toolchain/gcc] upgrade Linaro GCC to 4.5-2011.05-0 - thanks to Mark Mentovai

File size: 10.4 KB
  • gcc/config/arm/arm-cores.def

    a b ARM_CORE("strongarm", strongarm, 4, 
    7474ARM_CORE("strongarm110",  strongarm110, 4,                   FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) 
    7575ARM_CORE("strongarm1100", strongarm1100, 4,                  FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) 
    7676ARM_CORE("strongarm1110", strongarm1110, 4,                  FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul) 
     77ARM_CORE("fa526",         fa526,        4,                               FL_LDSCHED, fastmul) 
    7778 
    7879/* V4T Architecture Processors */ 
    7980ARM_CORE("arm7tdmi",      arm7tdmi,     4T,     FL_CO_PROC          , fastmul) 
  • gcc/config/arm/arm.md

    a b  
    435435 
    436436(define_attr "generic_sched" "yes,no" 
    437437  (const (if_then_else 
    438           (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4") 
     438          (ior (eq_attr "tune" "fa526,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4") 
    439439               (eq_attr "tune_cortexr4" "yes")) 
    440440          (const_string "no") 
    441441          (const_string "yes")))) 
     
    467467(include "arm1020e.md") 
    468468(include "arm1026ejs.md") 
    469469(include "arm1136jfs.md") 
     470(include "fa526.md") 
    470471(include "cortex-a5.md") 
    471472(include "cortex-a8.md") 
    472473(include "cortex-a9.md") 
  • gcc/config/arm/arm-tune.md

    a b  
    11;; -*- buffer-read-only: t -*- 
    22;; Generated automatically by gentune.sh from arm-cores.def 
    33(define_attr "tune" 
    4         "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" 
     4        "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" 
    55        (const (symbol_ref "((enum attr_tune) arm_tune)"))) 
  • gcc/config/arm/bpabi.h

    a b  
    5252/* The BPABI integer comparison routines return { -1, 0, 1 }.  */ 
    5353#define TARGET_LIB_INT_CMP_BIASED !TARGET_BPABI 
    5454 
    55 #define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}" 
     55#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*\ 
     56|march=armv4|mcpu=fa526:--fix-v4bx}" 
    5657 
    5758#define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5|mcpu=cortex-a8|mcpu=cortex-a9:%{!r:--be8}}}" 
    5859 
  • new file gcc/config/arm/fa526.md

    - +  
     1;; Faraday FA526 Pipeline Description 
     2;; Copyright (C) 2010 Free Software Foundation, Inc. 
     3;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. 
     4 
     5;; This file is part of GCC. 
     6;; 
     7;; GCC is free software; you can redistribute it and/or modify it under 
     8;; the terms of the GNU General Public License as published by the Free 
     9;; Software Foundation; either version 3, or (at your option) any later 
     10;; version. 
     11;; 
     12;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 
     13;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 
     14;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License 
     15;; for more details. 
     16;; 
     17;; You should have received a copy of the GNU General Public License 
     18;; along with GCC; see the file COPYING3.  If not see 
     19;; <http://www.gnu.org/licenses/>.  */ 
     20 
     21;; These descriptions are based on the information contained in the 
     22;; FA526 Core Design Note, Copyright (c) 2010 Faraday Technology Corp. 
     23;; 
     24;; Modeled pipeline characteristics: 
     25;; LD -> any use: latency = 3 (2 cycle penalty). 
     26;; ALU -> any use: latency = 2 (1 cycle penalty). 
     27 
     28;; This automaton provides a pipeline description for the Faraday 
     29;; FA526 core. 
     30;; 
     31;; The model given here assumes that the condition for all conditional 
     32;; instructions is "true", i.e., that all of the instructions are 
     33;; actually executed. 
     34 
     35(define_automaton "fa526") 
     36 
     37;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     38;; Pipelines 
     39;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     40 
     41;; There is a single pipeline 
     42;; 
     43;;   The ALU pipeline has fetch, decode, execute, memory, and 
     44;;   write stages.  We only need to model the execute, memory and write 
     45;;   stages. 
     46 
     47;;      S      E      M      W 
     48 
     49(define_cpu_unit "fa526_core" "fa526") 
     50 
     51;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     52;; ALU Instructions 
     53;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     54 
     55;; ALU instructions require two cycles to execute, and use the ALU 
     56;; pipeline in each of the three stages.  The results are available 
     57;; after the execute stage stage has finished. 
     58;; 
     59;; If the destination register is the PC, the pipelines are stalled 
     60;; for several cycles.  That case is not modeled here. 
     61 
     62;; ALU operations 
     63(define_insn_reservation "526_alu_op" 1 
     64 (and (eq_attr "tune" "fa526") 
     65      (eq_attr "type" "alu")) 
     66 "fa526_core") 
     67 
     68(define_insn_reservation "526_alu_shift_op" 2 
     69 (and (eq_attr "tune" "fa526") 
     70      (eq_attr "type" "alu_shift,alu_shift_reg")) 
     71 "fa526_core") 
     72 
     73;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     74;; Multiplication Instructions 
     75;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     76 
     77(define_insn_reservation "526_mult1" 2 
     78 (and (eq_attr "tune" "fa526") 
     79      (eq_attr "insn" "smlalxy,smulxy,smlaxy,smlalxy")) 
     80 "fa526_core") 
     81 
     82(define_insn_reservation "526_mult2" 5 
     83 (and (eq_attr "tune" "fa526") 
     84      (eq_attr "insn" "mul,mla,muls,mlas,umull,umlal,smull,smlal,umulls,\ 
     85                       umlals,smulls,smlals,smlawx")) 
     86 "fa526_core*4") 
     87 
     88;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     89;; Load/Store Instructions 
     90;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     91 
     92;; The models for load/store instructions do not accurately describe 
     93;; the difference between operations with a base register writeback 
     94;; (such as "ldm!").  These models assume that all memory references 
     95;; hit in dcache. 
     96 
     97(define_insn_reservation "526_load1_op" 3 
     98 (and (eq_attr "tune" "fa526") 
     99      (eq_attr "type" "load1,load_byte")) 
     100 "fa526_core") 
     101 
     102(define_insn_reservation "526_load2_op" 4 
     103 (and (eq_attr "tune" "fa526") 
     104      (eq_attr "type" "load2")) 
     105 "fa526_core*2") 
     106 
     107(define_insn_reservation "526_load3_op" 5 
     108 (and (eq_attr "tune" "fa526") 
     109      (eq_attr "type" "load3")) 
     110 "fa526_core*3") 
     111 
     112(define_insn_reservation "526_load4_op" 6 
     113 (and (eq_attr "tune" "fa526") 
     114      (eq_attr "type" "load4")) 
     115 "fa526_core*4") 
     116 
     117(define_insn_reservation "526_store1_op" 0 
     118 (and (eq_attr "tune" "fa526") 
     119      (eq_attr "type" "store1")) 
     120 "fa526_core") 
     121 
     122(define_insn_reservation "526_store2_op" 1 
     123 (and (eq_attr "tune" "fa526") 
     124      (eq_attr "type" "store2")) 
     125 "fa526_core*2") 
     126 
     127(define_insn_reservation "526_store3_op" 2 
     128 (and (eq_attr "tune" "fa526") 
     129      (eq_attr "type" "store3")) 
     130 "fa526_core*3") 
     131 
     132(define_insn_reservation "526_store4_op" 3 
     133 (and (eq_attr "tune" "fa526") 
     134      (eq_attr "type" "store4")) 
     135 "fa526_core*4") 
     136 
     137;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     138;; Branch and Call Instructions 
     139;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
     140 
     141;; Branch instructions are difficult to model accurately.  The FA526 
     142;; core can predict most branches.  If the branch is predicted 
     143;; correctly, and predicted early enough, the branch can be completely 
     144;; eliminated from the instruction stream.  Some branches can 
     145;; therefore appear to require zero cycle to execute.  We assume that 
     146;; all branches are predicted correctly, and that the latency is 
     147;; therefore the minimum value. 
     148 
     149(define_insn_reservation "526_branch_op" 0 
     150 (and (eq_attr "tune" "fa526") 
     151      (eq_attr "type" "branch")) 
     152 "fa526_core") 
     153 
     154;; The latency for a call is actually the latency when the result is available. 
     155;; i.e. R0 ready for int return value.  For most cases, the return value is set 
     156;; by a mov instruction, which has 1 cycle latency. 
     157(define_insn_reservation "526_call_op" 1 
     158 (and (eq_attr "tune" "fa526") 
     159      (eq_attr "type" "call")) 
     160 "fa526_core") 
     161 
  • gcc/config/arm/t-arm

    a b MD_INCLUDES= $(srcdir)/config/arm/arm-t 
    2323                $(srcdir)/config/arm/arm-generic.md             \ 
    2424                $(srcdir)/config/arm/arm1020e.md                \ 
    2525                $(srcdir)/config/arm/arm1026ejs.md              \ 
     26                $(srcdir)/config/arm/fa526.md                   \ 
    2627                $(srcdir)/config/arm/arm1136jfs.md              \ 
    2728                $(srcdir)/config/arm/arm926ejs.md               \ 
    2829                $(srcdir)/config/arm/cirrus.md                  \ 
  • gcc/config/arm/t-arm-elf

    a b MULTILIB_DIRNAMES = arm thumb 
    3636MULTILIB_EXCEPTIONS  =  
    3737MULTILIB_MATCHES     = 
    3838 
     39#MULTILIB_OPTIONS     += mcpu=fa526 
     40#MULTILIB_DIRNAMES    += fa526 
     41#MULTILIB_EXCEPTIONS  += *mthumb*/*mcpu=fa526 
     42 
    3943#MULTILIB_OPTIONS      += march=armv7 
    4044#MULTILIB_DIRNAMES     += thumb2 
    4145#MULTILIB_EXCEPTIONS   += march=armv7* marm/*march=armv7* 
    MULTILIB_MATCHES = 
    5256MULTILIB_OPTIONS       += mfloat-abi=hard 
    5357MULTILIB_DIRNAMES      += fpu 
    5458MULTILIB_EXCEPTIONS    += *mthumb/*mfloat-abi=hard* 
     59MULTILIB_EXCEPTIONS    += *mcpu=fa526/*mfloat-abi=hard* 
    5560 
    5661# MULTILIB_OPTIONS    += mcpu=ep9312 
    5762# MULTILIB_DIRNAMES   += ep9312 
  • gcc/doc/invoke.texi

    a b assembly code. Permissible names are: @ 
    99239923@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3}, 
    99249924@samp{cortex-m1}, 
    99259925@samp{cortex-m0}, 
    9926 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. 
     9926@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, 
     9927@samp{fa526}. 
    99279928 
    99289929@item -mtune=@var{name} 
    99299930@opindex mtune 
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