Changeset 10521


Ignore:
Timestamp:
2008-02-23T20:07:12+01:00 (8 years ago)
Author:
mb
Message:

More SSB GigE fixes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/brcm47xx/patches-2.6.23/700-ssb-gigabit-ethernet-driver.patch

    r10509 r10521  
    11Index: linux-2.6.23.16/drivers/ssb/Kconfig 
    22=================================================================== 
    3 --- linux-2.6.23.16.orig/drivers/ssb/Kconfig    2008-02-20 18:32:01.000000000 +0100 
    4 +++ linux-2.6.23.16/drivers/ssb/Kconfig 2008-02-20 18:32:31.000000000 +0100 
     3--- linux-2.6.23.16.orig/drivers/ssb/Kconfig    2008-02-22 19:40:57.000000000 +0100 
     4+++ linux-2.6.23.16/drivers/ssb/Kconfig 2008-02-22 19:42:52.000000000 +0100 
    55@@ -120,4 +120,13 @@ config SSB_DRIVER_EXTIF 
    66  
     
    1919Index: linux-2.6.23.16/drivers/ssb/Makefile 
    2020=================================================================== 
    21 --- linux-2.6.23.16.orig/drivers/ssb/Makefile   2008-02-20 18:32:01.000000000 +0100 
    22 +++ linux-2.6.23.16/drivers/ssb/Makefile        2008-02-20 18:32:31.000000000 +0100 
     21--- linux-2.6.23.16.orig/drivers/ssb/Makefile   2008-02-22 19:40:57.000000000 +0100 
     22+++ linux-2.6.23.16/drivers/ssb/Makefile        2008-02-22 19:42:52.000000000 +0100 
    2323@@ -11,6 +11,7 @@ ssb-y                                 += driver_chipcommon.o 
    2424 ssb-$(CONFIG_SSB_DRIVER_MIPS)          += driver_mipscore.o 
     
    3232=================================================================== 
    3333--- /dev/null   1970-01-01 00:00:00.000000000 +0000 
    34 +++ linux-2.6.23.16/drivers/ssb/driver_gige.c   2008-02-20 18:32:31.000000000 +0100 
    35 @@ -0,0 +1,268 @@ 
     34+++ linux-2.6.23.16/drivers/ssb/driver_gige.c   2008-02-22 20:59:46.000000000 +0100 
     35@@ -0,0 +1,281 @@ 
    3636+/* 
    3737+ * Sonics Silicon Backplane 
     
    203203+{ 
    204204+       struct ssb_gige *dev; 
    205 +       u32 base; 
     205+       u32 base, tmslow, tmshigh; 
    206206+ 
    207207+       dev = kzalloc(sizeof(*dev), GFP_KERNEL); 
     
    214214+       dev->pci_controller.io_resource = &dev->io_resource; 
    215215+       dev->pci_controller.mem_resource = &dev->mem_resource; 
    216 +       dev->pci_controller.mem_offset = 0x24000000; 
    217216+       dev->pci_controller.io_map_base = 0x800; 
    218217+       dev->pci_ops.read = ssb_gige_pci_read_config; 
    219218+       dev->pci_ops.write = ssb_gige_pci_write_config; 
    220219+ 
    221 +       dev->io_resource.name = "SSB GIGE I/O"; 
     220+       dev->io_resource.name = SSB_GIGE_IO_RES_NAME; 
    222221+       dev->io_resource.start = 0x800; 
    223222+       dev->io_resource.end = 0x8FF; 
     
    232231+       gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0); 
    233232+ 
    234 +       dev->mem_resource.name = "SSB GIGE memory"; 
     233+       dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME; 
    235234+       dev->mem_resource.start = base; 
    236 +       dev->mem_resource.end = base + SSB_CORE_SIZE - 1; 
     235+       dev->mem_resource.end = base + 0x10000 - 1; 
    237236+       dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; 
    238237+ 
     
    250249+       gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068); 
    251250+ 
    252 +       //TODO 
     251+       /* Check if we have an RGMII or GMII PHY-bus. 
     252+        * On RGMII do not bypass the DLLs */ 
     253+       tmslow = ssb_read32(sdev, SSB_TMSLOW); 
     254+       tmshigh = ssb_read32(sdev, SSB_TMSHIGH); 
     255+       if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) { 
     256+               tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS; 
     257+               tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS; 
     258+               dev->has_rgmii = 1; 
     259+       } else { 
     260+               tmslow |= SSB_GIGE_TMSLOW_TXBYPASS; 
     261+               tmslow |= SSB_GIGE_TMSLOW_RXBYPASS; 
     262+               dev->has_rgmii = 0; 
     263+       } 
     264+       tmslow |= SSB_GIGE_TMSLOW_DLLEN; 
     265+       ssb_write32(sdev, SSB_TMSLOW, tmslow); 
    253266+ 
    254267+       ssb_set_drvdata(sdev, dev); 
     
    305318=================================================================== 
    306319--- /dev/null   1970-01-01 00:00:00.000000000 +0000 
    307 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h 2008-02-20 18:32:31.000000000 +0100 
    308 @@ -0,0 +1,70 @@ 
     320+++ linux-2.6.23.16/include/linux/ssb/ssb_driver_gige.h 2008-02-22 20:47:58.000000000 +0100 
     321@@ -0,0 +1,178 @@ 
    309322+#ifndef LINUX_SSB_DRIVER_GIGE_H_ 
    310323+#define LINUX_SSB_DRIVER_GIGE_H_ 
    311324+ 
     325+#include <linux/ssb/ssb.h> 
    312326+#include <linux/pci.h> 
    313327+#include <linux/spinlock.h> 
    314328+ 
     329+ 
    315330+#ifdef CONFIG_SSB_DRIVER_GIGE 
     331+ 
    316332+ 
    317333+#define SSB_GIGE_PCIIO                 0x0000 /* PCI I/O Registers (1024 bytes) */ 
     
    325341+#define SSB_GIGE_SHIM_SIOCPMA          0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */ 
    326342+ 
     343+/* TM Status High flags */ 
     344+#define SSB_GIGE_TMSHIGH_RGMII         0x00010000 /* Have an RGMII PHY-bus */ 
     345+/* TM Status Low flags */ 
     346+#define SSB_GIGE_TMSLOW_TXBYPASS       0x00080000 /* TX bypass (no delay) */ 
     347+#define SSB_GIGE_TMSLOW_RXBYPASS       0x00100000 /* RX bypass (no delay) */ 
     348+#define SSB_GIGE_TMSLOW_DLLEN          0x01000000 /* Enable DLL controls */ 
     349+ 
     350+/* Boardflags (low) */ 
     351+#define SSB_GIGE_BFL_ROBOSWITCH                0x0010 
     352+ 
     353+ 
     354+#define SSB_GIGE_MEM_RES_NAME          "SSB Broadcom 47xx GigE memory" 
     355+#define SSB_GIGE_IO_RES_NAME           "SSB Broadcom 47xx GigE I/O" 
     356+ 
    327357+struct ssb_gige { 
    328358+       struct ssb_device *dev; 
    329359+ 
    330360+       spinlock_t lock; 
     361+ 
     362+       /* True, if the device has an RGMII bus. 
     363+        * False, if the device has a GMII bus. */ 
     364+       bool has_rgmii; 
    331365+ 
    332366+       /* The PCI controller device. */ 
     
    337371+}; 
    338372+ 
     373+/* Check whether a PCI device is a SSB Gigabit Ethernet core. */ 
     374+static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev) 
     375+{ 
     376+       return (pdev->resource[0].name && 
     377+               strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0); 
     378+} 
     379+ 
     380+/* Convert a pci_dev pointer to a ssb_gige pointer. */ 
     381+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev) 
     382+{ 
     383+       if (!pdev_is_ssb_gige_core(pdev)) 
     384+               return NULL; 
     385+       return container_of(pdev->bus->ops, struct ssb_gige, pci_ops); 
     386+} 
     387+ 
     388+/* Returns whether the PHY is connected by an RGMII bus. */ 
     389+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev) 
     390+{ 
     391+       struct ssb_gige *dev = pdev_to_ssb_gige(pdev); 
     392+       return (dev ? dev->has_rgmii : 0); 
     393+} 
     394+ 
     395+/* Returns whether we have a Roboswitch. */ 
     396+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev) 
     397+{ 
     398+       struct ssb_gige *dev = pdev_to_ssb_gige(pdev); 
     399+       if (dev) 
     400+               return !!(dev->dev->bus->sprom.boardflags_lo & 
     401+                         SSB_GIGE_BFL_ROBOSWITCH); 
     402+       return 0; 
     403+} 
     404+ 
     405+/* Returns whether we can only do one DMA at once. */ 
     406+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev) 
     407+{ 
     408+       struct ssb_gige *dev = pdev_to_ssb_gige(pdev); 
     409+       if (dev) 
     410+               return ((dev->dev->bus->chip_id == 0x4785) && 
     411+                       (dev->dev->bus->chip_rev < 2)); 
     412+       return 0; 
     413+} 
     414+ 
     415+/* Returns whether we must flush posted writes. */ 
     416+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev) 
     417+{ 
     418+       struct ssb_gige *dev = pdev_to_ssb_gige(pdev); 
     419+       if (dev) 
     420+               return (dev->dev->bus->chip_id == 0x4785); 
     421+       return 0; 
     422+} 
     423+ 
     424+extern char * nvram_get(const char *name); //FIXME 
     425+/* Get the device MAC address */ 
     426+static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr) 
     427+{ 
     428+#ifdef CONFIG_BCM947XX 
     429+       char *res = nvram_get("et0macaddr"); //FIXME 
     430+       if (res) 
     431+               memcpy(macaddr, res, 6); 
     432+#endif 
     433+} 
     434+ 
    339435+extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev, 
    340436+                                         struct pci_dev *pdev); 
     
    375471+} 
    376472+ 
     473+static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev) 
     474+{ 
     475+       return 0; 
     476+} 
     477+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev) 
     478+{ 
     479+       return NULL; 
     480+} 
     481+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev) 
     482+{ 
     483+       return 0; 
     484+} 
     485+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev) 
     486+{ 
     487+       return 0; 
     488+} 
     489+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev) 
     490+{ 
     491+       return 0; 
     492+} 
     493+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev) 
     494+{ 
     495+       return 0; 
     496+} 
     497+ 
    377498+#endif /* CONFIG_SSB_DRIVER_GIGE */ 
    378499+#endif /* LINUX_SSB_DRIVER_GIGE_H_ */ 
    379500Index: linux-2.6.23.16/drivers/ssb/driver_pcicore.c 
    380501=================================================================== 
    381 --- linux-2.6.23.16.orig/drivers/ssb/driver_pcicore.c   2008-02-20 18:32:01.000000000 +0100 
    382 +++ linux-2.6.23.16/drivers/ssb/driver_pcicore.c        2008-02-20 18:32:31.000000000 +0100 
     502--- linux-2.6.23.16.orig/drivers/ssb/driver_pcicore.c   2008-02-22 19:40:57.000000000 +0100 
     503+++ linux-2.6.23.16/drivers/ssb/driver_pcicore.c        2008-02-22 19:42:52.000000000 +0100 
    383504@@ -60,74 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock); 
    384505 /* Core to access the external PCI config space. Can only have one. */ 
     
    551672Index: linux-2.6.23.16/drivers/ssb/embedded.c 
    552673=================================================================== 
    553 --- linux-2.6.23.16.orig/drivers/ssb/embedded.c 2008-02-20 18:32:01.000000000 +0100 
    554 +++ linux-2.6.23.16/drivers/ssb/embedded.c      2008-02-20 18:32:31.000000000 +0100 
     674--- linux-2.6.23.16.orig/drivers/ssb/embedded.c 2008-02-22 19:40:57.000000000 +0100 
     675+++ linux-2.6.23.16/drivers/ssb/embedded.c      2008-02-22 19:42:52.000000000 +0100 
    555676@@ -10,6 +10,9 @@ 
    556677  
     
    656777Index: linux-2.6.23.16/include/linux/ssb/ssb.h 
    657778=================================================================== 
    658 --- linux-2.6.23.16.orig/include/linux/ssb/ssb.h        2008-02-20 18:32:01.000000000 +0100 
    659 +++ linux-2.6.23.16/include/linux/ssb/ssb.h     2008-02-20 18:32:31.000000000 +0100 
     779--- linux-2.6.23.16.orig/include/linux/ssb/ssb.h        2008-02-22 19:40:57.000000000 +0100 
     780+++ linux-2.6.23.16/include/linux/ssb/ssb.h     2008-02-22 19:42:52.000000000 +0100 
    660781@@ -422,5 +422,12 @@ extern int ssb_bus_powerup(struct ssb_bu 
    661782 extern u32 ssb_admatch_base(u32 adm); 
     
    673794Index: linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h 
    674795=================================================================== 
    675 --- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_pci.h     2008-02-20 18:32:01.000000000 +0100 
    676 +++ linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h  2008-02-20 18:32:31.000000000 +0100 
     796--- linux-2.6.23.16.orig/include/linux/ssb/ssb_driver_pci.h     2008-02-22 19:40:57.000000000 +0100 
     797+++ linux-2.6.23.16/include/linux/ssb/ssb_driver_pci.h  2008-02-22 19:42:52.000000000 +0100 
    677798@@ -1,6 +1,11 @@ 
    678799 #ifndef LINUX_SSB_PCICORE_H_ 
     
    716837Index: linux-2.6.23.16/drivers/ssb/main.c 
    717838=================================================================== 
    718 --- linux-2.6.23.16.orig/drivers/ssb/main.c     2008-02-20 18:32:01.000000000 +0100 
    719 +++ linux-2.6.23.16/drivers/ssb/main.c  2008-02-20 18:32:31.000000000 +0100 
     839--- linux-2.6.23.16.orig/drivers/ssb/main.c     2008-02-22 19:40:57.000000000 +0100 
     840+++ linux-2.6.23.16/drivers/ssb/main.c  2008-02-22 19:42:52.000000000 +0100 
    720841@@ -14,6 +14,7 @@ 
    721842 #include <linux/io.h> 
     
    778899Index: linux-2.6.23.16/drivers/ssb/ssb_private.h 
    779900=================================================================== 
    780 --- linux-2.6.23.16.orig/drivers/ssb/ssb_private.h      2008-02-20 18:32:01.000000000 +0100 
    781 +++ linux-2.6.23.16/drivers/ssb/ssb_private.h   2008-02-20 18:32:31.000000000 +0100 
     901--- linux-2.6.23.16.orig/drivers/ssb/ssb_private.h      2008-02-22 19:40:57.000000000 +0100 
     902+++ linux-2.6.23.16/drivers/ssb/ssb_private.h   2008-02-22 19:42:52.000000000 +0100 
    782903@@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty 
    783904 extern int ssb_devices_freeze(struct ssb_bus *bus); 
     
    789910 /* b43_pci_bridge.c */ 
    790911 #ifdef CONFIG_SSB_PCIHOST 
     912Index: linux-2.6.23.16/drivers/net/tg3.c 
     913=================================================================== 
     914--- linux-2.6.23.16.orig/drivers/net/tg3.c      2008-02-22 19:40:57.000000000 +0100 
     915+++ linux-2.6.23.16/drivers/net/tg3.c   2008-02-23 20:02:58.000000000 +0100 
     916@@ -38,6 +38,7 @@ 
     917 #include <linux/workqueue.h> 
     918 #include <linux/prefetch.h> 
     919 #include <linux/dma-mapping.h> 
     920+#include <linux/ssb/ssb_driver_gige.h> 
     921  
     922 #include <net/checksum.h> 
     923 #include <net/ip.h> 
     924@@ -410,8 +411,9 @@ static void _tw32_flush(struct tg3 *tp,  
     925 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) 
     926 { 
     927        tp->write32_mbox(tp, off, val); 
     928-       if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && 
     929-           !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) 
     930+       if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) || 
     931+           (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && 
     932+            !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))) 
     933                tp->read32_mbox(tp, off); 
     934 } 
     935  
     936@@ -1988,6 +1990,14 @@ static int tg3_setup_copper_phy(struct t 
     937                tp->link_config.active_duplex = current_duplex; 
     938        } 
     939  
     940+       if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) { 
     941+               current_link_up = 1; 
     942+               current_speed = SPEED_1000; //FIXME 
     943+               current_duplex = DUPLEX_FULL; 
     944+               tp->link_config.active_speed = current_speed; 
     945+               tp->link_config.active_duplex = current_duplex; 
     946+       } 
     947+ 
     948        if (current_link_up == 1 && 
     949            (tp->link_config.active_duplex == DUPLEX_FULL) && 
     950            (tp->link_config.autoneg == AUTONEG_ENABLE)) { 
     951@@ -4813,6 +4823,11 @@ static int tg3_poll_fw(struct tg3 *tp) 
     952        int i; 
     953        u32 val; 
     954  
     955+       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { 
     956+               /* We don't use firmware. */ 
     957+               return 0; 
     958+       } 
     959+ 
     960        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 
     961                /* Wait up to 20ms for init done. */ 
     962                for (i = 0; i < 200; i++) { 
     963@@ -5040,6 +5055,14 @@ static int tg3_chip_reset(struct tg3 *tp 
     964                tw32(0x5000, 0x400); 
     965        } 
     966  
     967+       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { 
     968+               /* BCM4785: In order to avoid repercussions from using potentially 
     969+                * defective internal ROM, stop the Rx RISC CPU, which is not 
     970+                * required. */ 
     971+               tg3_stop_fw(tp); 
     972+               tg3_halt_cpu(tp, RX_CPU_BASE); 
     973+       } 
     974+ 
     975        tw32(GRC_MODE, tp->grc_mode); 
     976  
     977        if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { 
     978@@ -5308,9 +5331,12 @@ static int tg3_halt_cpu(struct tg3 *tp,  
     979                return -ENODEV; 
     980        } 
     981  
     982-       /* Clear firmware's nvram arbitration. */ 
     983-       if (tp->tg3_flags & TG3_FLAG_NVRAM) 
     984-               tw32(NVRAM_SWARB, SWARB_REQ_CLR0); 
     985+       if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) { 
     986+               /* Clear firmware's nvram arbitration. */ 
     987+               if (tp->tg3_flags & TG3_FLAG_NVRAM) 
     988+                       tw32(NVRAM_SWARB, SWARB_REQ_CLR0); 
     989+       } 
     990+ 
     991        return 0; 
     992 } 
     993  
     994@@ -5391,6 +5417,11 @@ static int tg3_load_5701_a0_firmware_fix 
     995        struct fw_info info; 
     996        int err, i; 
     997  
     998+       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { 
     999+               /* We don't use firmware. */ 
     1000+               return 0; 
     1001+       } 
     1002+ 
     1003        info.text_base = TG3_FW_TEXT_ADDR; 
     1004        info.text_len = TG3_FW_TEXT_LEN; 
     1005        info.text_data = &tg3FwText[0]; 
     1006@@ -5949,6 +5980,11 @@ static int tg3_load_tso_firmware(struct  
     1007        unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; 
     1008        int err, i; 
     1009  
     1010+       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { 
     1011+               /* We don't use firmware. */ 
     1012+               return 0; 
     1013+       } 
     1014+ 
     1015        if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) 
     1016                return 0; 
     1017  
     1018@@ -6850,6 +6886,11 @@ static void tg3_timer(unsigned long __op 
     1019  
     1020        spin_lock(&tp->lock); 
     1021  
     1022+       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) { 
     1023+               /* BCM4785: Flush posted writes from GbE to host memory. */ 
     1024+               tr32(HOSTCC_MODE); 
     1025+       } 
     1026+ 
     1027        if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { 
     1028                /* All of this garbage is because when using non-tagged 
     1029                 * IRQ status the mailbox/status_block protocol the chip 
     1030@@ -8432,6 +8473,11 @@ static int tg3_test_nvram(struct tg3 *tp 
     1031        u32 *buf, csum, magic; 
     1032        int i, j, err = 0, size; 
     1033  
     1034+       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { 
     1035+               /* We don't have NVRAM. */ 
     1036+               return 0; 
     1037+       } 
     1038+ 
     1039        if (tg3_nvram_read_swab(tp, 0, &magic) != 0) 
     1040                return -EIO; 
     1041  
     1042@@ -9571,6 +9617,12 @@ static void __devinit tg3_get_5906_nvram 
     1043 /* Chips other than 5700/5701 use the NVRAM for fetching info. */ 
     1044 static void __devinit tg3_nvram_init(struct tg3 *tp) 
     1045 { 
     1046+       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) { 
     1047+               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */ 
     1048+               tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); 
     1049+               return; 
     1050+       } 
     1051+ 
     1052        tw32_f(GRC_EEPROM_ADDR, 
     1053             (EEPROM_ADDR_FSM_RESET | 
     1054              (EEPROM_DEFAULT_CLOCK_PERIOD << 
     1055@@ -9706,6 +9758,9 @@ static int tg3_nvram_read(struct tg3 *tp 
     1056 { 
     1057        int ret; 
     1058  
     1059+       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) 
     1060+               return -ENODEV; 
     1061+ 
     1062        if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) 
     1063                return tg3_nvram_read_using_eeprom(tp, offset, val); 
     1064  
     1065@@ -9938,6 +9993,9 @@ static int tg3_nvram_write_block(struct  
     1066 { 
     1067        int ret; 
     1068  
     1069+       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) 
     1070+               return -ENODEV; 
     1071+ 
     1072        if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { 
     1073                tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & 
     1074                       ~GRC_LCLCTRL_GPIO_OUTPUT1); 
     1075@@ -10804,7 +10862,6 @@ static int __devinit tg3_get_invariants( 
     1076                tp->write32 = tg3_write_flush_reg32; 
     1077        } 
     1078  
     1079- 
     1080        if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || 
     1081            (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { 
     1082                tp->write32_tx_mbox = tg3_write32_tx_mbox; 
     1083@@ -10840,6 +10897,11 @@ static int __devinit tg3_get_invariants( 
     1084              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) 
     1085                tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; 
     1086  
     1087+       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) { 
     1088+               tp->write32_tx_mbox = tg3_write_flush_reg32; 
     1089+               tp->write32_rx_mbox = tg3_write_flush_reg32; 
     1090+       } 
     1091+ 
     1092        /* Get eeprom hw config before calling tg3_set_power_state(). 
     1093         * In particular, the TG3_FLG2_IS_NIC flag must be 
     1094         * determined before calling tg3_set_power_state() so that 
     1095@@ -11184,6 +11246,10 @@ static int __devinit tg3_get_device_addr 
     1096        } 
     1097  
     1098        if (!is_valid_ether_addr(&dev->dev_addr[0])) { 
     1099+               if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) 
     1100+                       ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]); 
     1101+       } 
     1102+       if (!is_valid_ether_addr(&dev->dev_addr[0])) { 
     1103 #ifdef CONFIG_SPARC64 
     1104                if (!tg3_get_default_macaddr_sparc(tp)) 
     1105                        return 0; 
     1106@@ -11675,6 +11741,7 @@ static char * __devinit tg3_phy_string(s 
     1107        case PHY_ID_BCM5704:    return "5704"; 
     1108        case PHY_ID_BCM5705:    return "5705"; 
     1109        case PHY_ID_BCM5750:    return "5750"; 
     1110+       case PHY_ID_BCM5750_2:  return "5750-2"; 
     1111        case PHY_ID_BCM5752:    return "5752"; 
     1112        case PHY_ID_BCM5714:    return "5714"; 
     1113        case PHY_ID_BCM5780:    return "5780"; 
     1114@@ -11859,6 +11926,13 @@ static int __devinit tg3_init_one(struct 
     1115                tp->msg_enable = tg3_debug; 
     1116        else 
     1117                tp->msg_enable = TG3_DEF_MSG_ENABLE; 
     1118+       if (pdev_is_ssb_gige_core(pdev)) { 
     1119+               tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE; 
     1120+               if (ssb_gige_must_flush_posted_writes(pdev)) 
     1121+                       tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES; 
     1122+               if (ssb_gige_have_roboswitch(pdev)) 
     1123+                       tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH; 
     1124+       } 
     1125  
     1126        /* The word/byte swap controls here control register access byte 
     1127         * swapping.  DMA data byte swapping is controlled in the GRC_MODE 
     1128Index: linux-2.6.23.16/drivers/net/tg3.h 
     1129=================================================================== 
     1130--- linux-2.6.23.16.orig/drivers/net/tg3.h      2008-02-22 19:40:57.000000000 +0100 
     1131+++ linux-2.6.23.16/drivers/net/tg3.h   2008-02-23 19:35:15.000000000 +0100 
     1132@@ -2279,6 +2279,10 @@ struct tg3 { 
     1133 #define TG3_FLG2_PHY_JITTER_BUG                0x20000000 
     1134 #define TG3_FLG2_NO_FWARE_REPORTED     0x40000000 
     1135 #define TG3_FLG2_PHY_ADJUST_TRIM       0x80000000 
     1136+       u32                             tg3_flags3; 
     1137+#define TG3_FLG3_IS_SSB_CORE           0x00000001 
     1138+#define TG3_FLG3_FLUSH_POSTED_WRITES   0x00000002 
     1139+#define TG3_FLG3_ROBOSWITCH            0x00000004 
     1140  
     1141        struct timer_list               timer; 
     1142        u16                             timer_counter; 
     1143@@ -2333,6 +2337,7 @@ struct tg3 { 
     1144 #define PHY_ID_BCM5714                 0x60008340 
     1145 #define PHY_ID_BCM5780                 0x60008350 
     1146 #define PHY_ID_BCM5755                 0xbc050cc0 
     1147+#define PHY_ID_BCM5750_2               0xbc050cd0 
     1148 #define PHY_ID_BCM5787                 0xbc050ce0 
     1149 #define PHY_ID_BCM5756                 0xbc050ed0 
     1150 #define PHY_ID_BCM5906                 0xdc00ac40 
     1151@@ -2364,7 +2369,8 @@ struct tg3 { 
     1152         (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \ 
     1153         (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \ 
     1154         (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \ 
     1155-        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002) 
     1156+        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002 || \ 
     1157+        (X) == PHY_ID_BCM5750_2) 
     1158  
     1159        struct tg3_hw_stats             *hw_stats; 
     1160        dma_addr_t                      stats_mapping; 
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