Changeset 12617


Ignore:
Timestamp:
2008-09-17T15:29:47+02:00 (8 years ago)
Author:
juhosg
Message:

[ar71xx] fix the PCI byte lane enable generation code, based on a patch by Chris Dearman

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c

    r11894 r12617  
    6060/* Byte lane enable bits */ 
    6161static u8 ble_table[4][4] = { 
    62         {0xf, 0xe, 0xd, 0xc}, 
    63         {0xc, 0x9, 0x3, 0x1}, 
    64         {0x0, 0x0, 0x0, 0x0}, 
    65         {0x0, 0x0, 0x0, 0x0}, 
     62        {0x0, 0xf, 0xf, 0xf}, 
     63        {0xe, 0xd, 0xb, 0x7}, 
     64        {0xc, 0xf, 0x3, 0xf}, 
     65        {0xf, 0xf, 0xf, 0xf}, 
    6666}; 
    6767 
     
    7070        u32 t; 
    7171 
    72         t = ble_table[size][where & 3]; 
     72        t = ble_table[size & 3][where & 3]; 
     73        BUG_ON(t == 0xf); 
    7374        t <<= (local) ? 20 : 4; 
    7475        return t; 
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