Changeset 14373


Ignore:
Timestamp:
2009-02-02T21:00:04+01:00 (7 years ago)
Author:
mb
Message:

bcm47xx: Implement 4312 and part of 4325 PLL init.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/brcm47xx/patches-2.6.28/810-ssb-add-pmu-support.patch

    r14350 r14373  
    1414=================================================================== 
    1515--- /dev/null   1970-01-01 00:00:00.000000000 +0000 
    16 +++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c  2009-02-01 21:16:15.000000000 +0100 
    17 @@ -0,0 +1,378 @@ 
     16+++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c  2009-02-02 20:57:13.000000000 +0100 
     17@@ -0,0 +1,481 @@ 
    1818+/* 
    1919+ * Sonics Silicon Backplane 
     
    177177+} 
    178178+ 
     179+struct pmu1_plltab_entry { 
     180+       u16 freq;       /* Crystal frequency in kHz.*/ 
     181+       u8 xf;          /* Crystal frequency value for PMU control */ 
     182+       u8 ndiv_int; 
     183+       u32 ndiv_frac; 
     184+       u8 p1div; 
     185+       u8 p2div; 
     186+}; 
     187+ 
     188+static const struct pmu1_plltab_entry pmu1_plltab[] = { 
     189+       { .freq = 12000, .xf =  1, .p1div = 3, .p2div = 22, .ndiv_int =  0x9, .ndiv_frac = 0xFFFFEF, }, 
     190+       { .freq = 13000, .xf =  2, .p1div = 1, .p2div =  6, .ndiv_int =  0xb, .ndiv_frac = 0x483483, }, 
     191+       { .freq = 14400, .xf =  3, .p1div = 1, .p2div = 10, .ndiv_int =  0xa, .ndiv_frac = 0x1C71C7, }, 
     192+       { .freq = 15360, .xf =  4, .p1div = 1, .p2div =  5, .ndiv_int =  0xb, .ndiv_frac = 0x755555, }, 
     193+       { .freq = 16200, .xf =  5, .p1div = 1, .p2div = 10, .ndiv_int =  0x5, .ndiv_frac = 0x6E9E06, }, 
     194+       { .freq = 16800, .xf =  6, .p1div = 1, .p2div = 10, .ndiv_int =  0x5, .ndiv_frac = 0x3CF3CF, }, 
     195+       { .freq = 19200, .xf =  7, .p1div = 1, .p2div =  9, .ndiv_int =  0x5, .ndiv_frac = 0x17B425, }, 
     196+       { .freq = 19800, .xf =  8, .p1div = 1, .p2div = 11, .ndiv_int =  0x4, .ndiv_frac = 0xA57EB,  }, 
     197+       { .freq = 20000, .xf =  9, .p1div = 1, .p2div = 11, .ndiv_int =  0x4, .ndiv_frac = 0,        }, 
     198+       { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int =  0xa, .ndiv_frac = 0,        }, 
     199+       { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int =  0xb, .ndiv_frac = 0,        }, 
     200+       { .freq = 26000, .xf = 12, .p1div = 1, .p2div =  2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, }, 
     201+       { .freq = 30000, .xf = 13, .p1div = 3, .p2div =  8, .ndiv_int =  0xb, .ndiv_frac = 0,        }, 
     202+       { .freq = 38400, .xf = 14, .p1div = 1, .p2div =  5, .ndiv_int =  0x4, .ndiv_frac = 0x955555, }, 
     203+       { .freq = 40000, .xf = 15, .p1div = 1, .p2div =  2, .ndiv_int =  0xb, .ndiv_frac = 0,        }, 
     204+}; 
     205+ 
     206+#define SSB_PMU1_DEFAULT_XTALFREQ      15360 
     207+ 
     208+static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq) 
     209+{ 
     210+       const struct pmu1_plltab_entry *e; 
     211+       unsigned int i; 
     212+ 
     213+       for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) { 
     214+               e = &pmu1_plltab[i]; 
     215+               if (e->freq == crystalfreq) 
     216+                       return e; 
     217+       } 
     218+ 
     219+       return NULL; 
     220+} 
     221+ 
    179222+/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */ 
    180223+static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc, 
    181224+                               u32 crystalfreq) 
    182225+{ 
    183 +       WARN_ON(1); 
     226+       struct ssb_bus *bus = cc->dev->bus; 
     227+       const struct pmu1_plltab_entry *e = NULL; 
     228+       u32 buffer_strength = 0; 
     229+       u32 tmp, pllctl, pmuctl; 
     230+       unsigned int i; 
     231+ 
     232+       if (bus->chip_id == 0x4312) { 
     233+               /* We do not touch the BCM4312 PLL and assume 
     234+                * the default crystal settings work out-of-the-box. */ 
     235+               cc->pmu.crystalfreq = 20000; 
     236+               return; 
     237+       } 
     238+ 
     239+       if (crystalfreq) 
     240+               e = pmu1_plltab_find_entry(crystalfreq); 
     241+       if (!e) 
     242+               e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ); 
     243+       BUG_ON(!e); 
     244+       crystalfreq = e->freq; 
     245+       cc->pmu.crystalfreq = e->freq; 
     246+ 
     247+       /* Check if the PLL already is programmed to this frequency. */ 
     248+       pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); 
     249+       if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) { 
     250+               /* We're already there... */ 
     251+               return; 
     252+       } 
     253+ 
     254+       ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n", 
     255+                  (crystalfreq / 1000), (crystalfreq % 1000)); 
     256+ 
     257+WARN_ON(1); //TODO not fully implemented, yet. 
     258+return; 
     259+       /* First turn the PLL off. */ 
     260+       switch (bus->chip_id) { 
     261+       case 0x4325: 
     262+               chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 
     263+                             ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) | 
     264+                               (1 << SSB_PLLRES_4325_HT_AVAIL))); 
     265+               chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, 
     266+                             ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) | 
     267+                               (1 << SSB_PLLRES_4325_HT_AVAIL))); 
     268+               /* Adjust the BBPLL to 2 on all channels later. */ 
     269+               buffer_strength = 0x222222; 
     270+               break; 
     271+       default: 
     272+               SSB_WARN_ON(1); 
     273+       } 
     274+       for (i = 1500; i; i--) { 
     275+               tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); 
     276+               if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)) 
     277+                       break; 
     278+               udelay(10); 
     279+       } 
     280+       tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); 
     281+       if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT) 
     282+               ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n"); 
     283+ 
     284+       /* Set p1div and p2div. */ 
     285+       pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0); 
     286+       //TODO 
     287+       ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl); 
     288+ 
    184289+       //TODO 
    185290+} 
     
    370475+       struct ssb_bus *bus = cc->dev->bus; 
    371476+       u32 pmucap; 
    372 + 
    373 +if (bus->chip_id != 0x5354) return; //FIXME currently only 5354 code implemented. 
    374477+ 
    375478+       if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU)) 
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