Changeset 16821


Ignore:
Timestamp:
2009-07-12T22:24:18+02:00 (7 years ago)
Author:
lars
Message:

[s3c24xx] glamo: get rid of static driver handle.

Location:
trunk/target/linux
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/generic-2.6/files-2.6.30/include/linux/glamofb.h

    r16816 r16821  
    3333 
    3434#ifdef CONFIG_MFD_GLAMO 
    35 void glamo_lcm_reset(int level); 
     35void glamo_lcm_reset(struct platform_device *pdev, int level); 
    3636#else 
    3737#define glamo_lcm_reset(...) do {} while (0) 
  • trunk/target/linux/s3c24xx/files-2.6.30/arch/arm/mach-s3c2442/mach-gta02.c

    r16816 r16821  
    10831083static void gta02_jbt6k74_reset(int devidx, int level) 
    10841084{ 
    1085         glamo_lcm_reset(level); 
     1085        glamo_lcm_reset(&gta02_glamo_dev, level); 
    10861086}        
    10871087 
  • trunk/target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-core.c

    r16816 r16821  
    9999}; 
    100100 
    101 static struct glamo_core *glamo_handle; 
    102  
    103101static inline void __reg_write(struct glamo_core *glamo, 
    104102                                u_int16_t reg, u_int16_t val) 
     
    221219static void glamo_ack_irq(unsigned int irq) 
    222220{ 
     221        struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq); 
    223222        /* clear interrupt source */ 
    224         __reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR, 
     223        __reg_write(glamo, GLAMO_REG_IRQ_CLEAR, 
    225224                    1 << irq2glamo(irq)); 
    226225} 
     
    228227static void glamo_mask_irq(unsigned int irq) 
    229228{ 
     229        struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq); 
    230230        u_int16_t tmp; 
    231231 
    232232        /* clear bit in enable register */ 
    233         tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE); 
     233        tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE); 
    234234        tmp &= ~(1 << irq2glamo(irq)); 
    235         __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp); 
     235        __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp); 
    236236} 
    237237 
    238238static void glamo_unmask_irq(unsigned int irq) 
    239239{ 
     240        struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq); 
    240241        u_int16_t tmp; 
    241242 
    242243        /* set bit in enable register */ 
    243         tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE); 
     244        tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE); 
    244245        tmp |= (1 << irq2glamo(irq)); 
    245         __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp); 
     246        __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp); 
    246247} 
    247248 
    248249static struct irq_chip glamo_irq_chip = { 
     250        .name   = "glamo", 
    249251        .ack    = glamo_ack_irq, 
    250252        .mask   = glamo_mask_irq, 
     
    254256static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc) 
    255257{ 
     258        struct glamo_core *glamo = get_irq_desc_chip_data(desc); 
    256259        desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); 
    257260 
     
    282285 
    283286                /* read IRQ status register */ 
    284                 irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS); 
     287                irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS); 
    285288                for (i = 0; i < 9; i++) 
    286289                        if (irqstatus & (1 << i)) 
     
    597600EXPORT_SYMBOL_GPL(glamo_engine_reset); 
    598601 
    599 void glamo_lcm_reset(int level) 
    600 { 
    601         if (!glamo_handle) 
     602void glamo_lcm_reset(struct platform_device *pdev, int level) 
     603{ 
     604        struct glamo_core *glamo = dev_get_drvdata(&pdev->dev); 
     605        if (!glamo) 
    602606                return; 
    603607 
    604         glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level); 
    605         glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT); 
    606  
     608        glamo_gpio_setpin(glamo, GLAMO_GPIO4, level); 
     609        glamo_gpio_cfgpin(glamo, GLAMO_GPIO4_OUTPUT); 
    607610} 
    608611EXPORT_SYMBOL_GPL(glamo_lcm_reset); 
     
    11081111        struct glamo_core *glamo; 
    11091112 
    1110         if (glamo_handle) { 
    1111                 dev_err(&pdev->dev, 
    1112                         "This driver supports only one instance\n"); 
    1113                 return -EBUSY; 
    1114         } 
    1115  
    11161113        glamo = kmalloc(GFP_KERNEL, sizeof(*glamo)); 
    11171114        if (!glamo) 
     
    11191116 
    11201117        spin_lock_init(&glamo->lock); 
    1121         glamo_handle = glamo; 
    11221118        glamo->pdev = pdev; 
    11231119        glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 
     
    11531149 
    11541150        for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) { 
    1155                 set_irq_chip(irq, &glamo_irq_chip); 
    1156                 set_irq_handler(irq, handle_level_irq); 
     1151                set_irq_chip_and_handler(irq, &glamo_irq_chip, handle_level_irq); 
    11571152                set_irq_flags(irq, IRQF_VALID); 
     1153                set_irq_chip_data(irq, glamo); 
    11581154        } 
    11591155 
     
    11621158                set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler); 
    11631159                set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING); 
     1160                set_irq_chip_data(glamo->irq, glamo); 
    11641161                dev_info(&pdev->dev, "Glamo interrupt registered\n"); 
    11651162                glamo->irq_works = 1; 
     
    12321229        disable_irq(glamo->irq); 
    12331230        set_irq_chained_handler(glamo->irq, NULL); 
     1231        set_irq_chip_data(glamo->irq, NULL); 
    12341232 
    12351233        for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) { 
    12361234                set_irq_flags(irq, 0); 
    12371235                set_irq_chip(irq, NULL); 
     1236                set_irq_chip_data(irq, NULL); 
    12381237        } 
    12391238 
     
    12411240bail_free: 
    12421241        platform_set_drvdata(pdev, NULL); 
    1243         glamo_handle = NULL; 
    12441242        kfree(glamo); 
    12451243 
     
    12541252        disable_irq(glamo->irq); 
    12551253        set_irq_chained_handler(glamo->irq, NULL); 
     1254        set_irq_chip_data(glamo->irq, NULL); 
    12561255 
    12571256        for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) { 
    12581257                set_irq_flags(irq, 0); 
    12591258                set_irq_chip(irq, NULL); 
     1259                set_irq_chip_data(irq, NULL); 
    12601260        } 
    12611261 
     
    12641264        iounmap(glamo->base); 
    12651265        release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP); 
    1266         glamo_handle = NULL; 
    12671266        kfree(glamo); 
    12681267 
     
    12741273static int glamo_suspend(struct platform_device *pdev, pm_message_t state) 
    12751274{ 
    1276         glamo_handle->suspending = 1; 
    1277         glamo_power(glamo_handle, GLAMO_POWER_SUSPEND); 
     1275        struct glamo_core *glamo = dev_get_drvdata(&pdev->dev); 
     1276        glamo->suspending = 1; 
     1277        glamo_power(glamo, GLAMO_POWER_SUSPEND); 
    12781278 
    12791279        return 0; 
     
    12821282static int glamo_resume(struct platform_device *pdev) 
    12831283{ 
    1284         glamo_power(glamo_handle, GLAMO_POWER_ON); 
    1285         glamo_handle->suspending = 0; 
     1284        struct glamo_core *glamo = dev_get_drvdata(&pdev->dev); 
     1285        glamo_power(glamo, GLAMO_POWER_ON); 
     1286        glamo->suspending = 0; 
    12861287 
    12871288        return 0; 
  • trunk/target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-mci.c

    r16816 r16821  
    220220                             GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 
    221221                       host->pdata->pglamo->base + GLAMO_REG_CLOCK_GEN5_1); 
    222                 mdelay(5); 
    223222        } 
    224223        spin_unlock_irqrestore(&host->pdata->pglamo->lock, flags); 
     224        mdelay(5); 
    225225} 
    226226 
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