Changeset 21143


Ignore:
Timestamp:
2010-04-24T19:24:11+02:00 (7 years ago)
Author:
nbd
Message:

ar71xx: fix a wifi card stability issue

when we receive a pci/ahb interrupt, we need to flush pending data for dma
from the device, otherwise the tx path may get stuck if the completion flag
of the dma descriptor is not updated at the time the tx interrupt arrives.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

    r20494 r21143  
    2222#include <asm/mach-ar71xx/ar71xx.h> 
    2323 
     24static int ip2_flush_reg; 
     25 
    2426static void ar71xx_gpio_irq_dispatch(void) 
    2527{ 
     
    240242                do_IRQ(AR71XX_CPU_IRQ_TIMER); 
    241243 
    242         else if (pending & STATUSF_IP2) 
     244        else if (pending & STATUSF_IP2) { 
     245                /* 
     246                 * This IRQ is meant for a PCI device. Drivers for PCI devices 
     247                 * typically allocate coherent DMA memory for the descriptor 
     248                 * ring, however the DMA controller may still have some 
     249                 * unsynchronized data in the FIFO. 
     250                 * Issue a flush here to ensure that the driver sees the update. 
     251                 */ 
     252                ar71xx_ddr_flush(ip2_flush_reg); 
    243253                do_IRQ(AR71XX_CPU_IRQ_IP2); 
     254        } 
    244255 
    245256        else if (pending & STATUSF_IP4) 
     
    261272void __init arch_init_irq(void) 
    262273{ 
     274        switch(ar71xx_soc) { 
     275        case AR71XX_SOC_AR7240: 
     276        case AR71XX_SOC_AR7241: 
     277        case AR71XX_SOC_AR7242: 
     278                ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; 
     279                break; 
     280        case AR71XX_SOC_AR9130: 
     281        case AR71XX_SOC_AR9132: 
     282                ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC; 
     283                break; 
     284        default: 
     285                ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; 
     286                break; 
     287        } 
    263288        mips_cpu_irq_init(); 
    264289 
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