Ignore:
Timestamp:
2010-07-24T02:18:58+02:00 (6 years ago)
Author:
acoul
Message:

ixp4xx: add kernel 2.6.34 preliminary support

Location:
trunk/target/linux/ixp4xx/patches-2.6.34
Files:
1 edited
1 copied

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ixp4xx/patches-2.6.34/050-disable_dmabounce.patch

    r21891 r22373  
    1 --- a/arch/arm/Kconfig 
    2 +++ b/arch/arm/Kconfig 
    3 @@ -417,7 +417,6 @@ config ARCH_IXP4XX 
     1--- a/arch/arm/Kconfig  2010-05-17 19:51:29.000000000 +0200 
     2+++ b/arch/arm/Kconfig  2010-05-18 17:44:39.000000000 +0200 
     3@@ -433,7 +433,6 @@ config ARCH_IXP4XX 
    44        select GENERIC_GPIO 
    55        select GENERIC_TIME 
     
    99          Support for Intel's IXP4XX (XScale) family of processors. 
    1010  
    11 --- a/arch/arm/mach-ixp4xx/Kconfig 
    12 +++ b/arch/arm/mach-ixp4xx/Kconfig 
    13 @@ -199,6 +199,45 @@ config IXP4XX_INDIRECT_PCI 
     11--- a/arch/arm/mach-ixp4xx/Kconfig      2010-02-25 14:45:00.000000000 +0100 
     12+++ b/arch/arm/mach-ixp4xx/Kconfig      2010-05-18 17:44:39.000000000 +0200 
     13@@ -199,6 +199,43 @@ config IXP4XX_INDIRECT_PCI 
    1414          need to use the indirect method instead. If you don't know 
    1515          what you need, leave this option unselected. 
    1616  
    1717+config IXP4XX_LEGACY_DMABOUNCE 
    18 +       bool "legacy PCI DMA bounce support" 
     18+       bool "Legacy PCI DMA bounce support" 
    1919+       depends on PCI 
    2020+       default n 
     
    2222+       help 
    2323+         The IXP4xx is limited to a 64MB window for PCI DMA, which 
    24 +         requires that PCI accesses above 64MB are bounced via buffers 
    25 +         below 64MB. Furthermore the IXP4xx has an erratum where PCI 
    26 +         read prefetches just below the 64MB limit can trigger lockups. 
     24+         requires that PCI accesses >= 64MB are bounced via buffers 
     25+         below 64MB. 
    2726+ 
    28 +         The kernel has traditionally handled these two issue by using 
    29 +         ARM specific DMA bounce support code for all accesses >= 64MB. 
     27+         The kernel has traditionally handled this issue by using ARM 
     28+         specific DMA bounce support code for all accesses >= 64MB. 
    3029+         That code causes problems of its own, so it is desirable to 
    31 +         disable it. As the kernel now has a workaround for the PCI read 
    32 +         prefetch erratum, it no longer requires the ARM bounce code. 
     30+         disable it. 
    3331+ 
    3432+         Enabling this option makes IXP4xx continue to use the problematic 
     
    5755        tristate "IXP4xx Queue Manager support" 
    5856        help 
    59 --- a/arch/arm/mach-ixp4xx/common-pci.c 
    60 +++ b/arch/arm/mach-ixp4xx/common-pci.c 
    61 @@ -321,27 +321,38 @@ static int abort_handler(unsigned long a 
     57--- a/arch/arm/mach-ixp4xx/common-pci.c 2010-05-17 19:51:29.000000000 +0200 
     58+++ b/arch/arm/mach-ixp4xx/common-pci.c 2010-05-18 17:44:39.000000000 +0200 
     59@@ -321,27 +321,33 @@ static int abort_handler(unsigned long a 
    6260  */ 
    6361 static int ixp4xx_pci_platform_notify(struct device *dev) 
     
    8987 int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) 
    9088 { 
    91 +       /* Note that this returns true for the last page below 64M due to 
    92 +        * IXP4xx erratum 15 (SCR 1289), which states that PCI prefetches 
    93 +        * can cross the boundary between valid memory and a reserved region 
    94 +        * causing AHB bus errors and a lock-up. 
    95 +        */ 
    96         return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); 
     89-       return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); 
     90+       return (dev->bus == &pci_bus_type ) && ((dma_addr + size) > SZ_64M); 
    9791 } 
    9892+#endif 
     
    10296  * Only first 64MB of memory can be accessed via PCI. 
    10397  * We use GFP_DMA to allocate safe buffers to do map/unmap. 
    104 @@ -364,6 +375,7 @@ void __init ixp4xx_adjust_zones(int node 
     98@@ -364,6 +370,7 @@ void __init ixp4xx_adjust_zones(int node 
    10599        zhole_size[1] = zhole_size[0]; 
    106100        zhole_size[0] = 0; 
     
    110104 void __init ixp4xx_pci_preinit(void) 
    111105 { 
    112 @@ -513,19 +525,35 @@ struct pci_bus * __devinit ixp4xx_scan_b 
    113  int 
    114  pci_set_dma_mask(struct pci_dev *dev, u64 mask) 
    115  { 
    116 -       if (mask >= SZ_64M - 1 ) 
    117 +#ifdef CONFIG_DMABOUNCE 
    118 +       if (mask >= SZ_64M - 1) 
    119                 return 0; 
    120   
    121         return -EIO; 
    122 +#else 
    123 +       /* Only honour masks < SZ_64M. Silently ignore masks >= SZ_64M 
    124 +          as generic drivers do not know about IXP4xx PCI DMA quirks. */ 
    125 +       if (mask < SZ_64M) 
    126 +               dev->dma_mask = mask; 
    127 +       return 0; 
    128 +#endif 
    129  } 
    130       
    131  int 
    132  pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 
    133  { 
    134 -       if (mask >= SZ_64M - 1 ) 
    135 +#ifdef CONFIG_DMABOUNCE 
    136 +       if (mask >= SZ_64M - 1) 
    137                 return 0; 
    138   
    139         return -EIO; 
    140 +#else 
    141 +       /* Only honour masks < SZ_64M. Silently ignore masks >= SZ_64M 
    142 +          as generic drivers do not know about IXP4xx PCI DMA quirks. */ 
    143 +       if (mask < SZ_64M) 
    144 +               dev->dev.coherent_dma_mask = mask; 
    145 +       return 0; 
    146 +#endif 
    147  } 
    148   
    149  EXPORT_SYMBOL(ixp4xx_pci_read); 
    150 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h 
    151 +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h 
     106--- a/arch/arm/mach-ixp4xx/include/mach/memory.h        2009-03-24 18:00:31.000000000 +0100 
     107+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h        2010-05-18 17:44:39.000000000 +0200 
    152108@@ -16,10 +16,12 @@ 
    153109  
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