Ignore:
Timestamp:
2011-06-01T00:53:20+02:00 (6 years ago)
Author:
juhosg
Message:

ar71xx: Fix header offset for newer WRT160NL models

Newer WRT160NLs have a flash chip with 4K erase blocks instead of 64K,
resulting in miscalculated partition sizes.
Since the actual sizes did not change, hardcode them to their current
sizes, and make sure they are at least one erase block big (in case Cisco
decides to start to use chips with 128K erase blocks).

Signed-off-by: Jonas Gorski <jonas.gorski+openwrt@…>

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/target/linux/ar71xx/files/drivers/mtd/wrt160nl_part.c

    r23977 r27049  
    7979static struct mtd_partition trx_parts[TRX_PARTS]; 
    8080 
     81#define WRT160NL_UBOOT_LEN      0x40000 
     82#define WRT160NL_ART_LEN        0x10000 
     83#define WRT160NL_NVRAM_LEN      0x10000 
     84 
    8185static int wrt160nl_parse_partitions(struct mtd_info *master, 
    8286                                     struct mtd_partition **pparts, 
     
    8892        size_t retlen; 
    8993        unsigned int kernel_len; 
     94        unsigned int uboot_len = max(master->erasesize, WRT160NL_UBOOT_LEN); 
     95        unsigned int nvram_len = max(master->erasesize, WRT160NL_NVRAM_LEN); 
     96        unsigned int art_len = max(master->erasesize, WRT160NL_ART_LEN); 
    9097        int ret; 
    9198 
     
    96103        } 
    97104 
    98         ret = master->read(master, 4 * master->erasesize, sizeof(*header), 
     105        ret = master->read(master, uboot_len, sizeof(*header), 
    99106                           &retlen, (void *) header); 
    100107        if (ret) 
     
    129136        trx_parts[0].name = "u-boot"; 
    130137        trx_parts[0].offset = 0; 
    131         trx_parts[0].size = 4 * master->erasesize; 
     138        trx_parts[0].size = uboot_len; 
    132139        trx_parts[0].mask_flags = MTD_WRITEABLE; 
    133140 
     
    139146        trx_parts[2].name = "rootfs"; 
    140147        trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; 
    141         trx_parts[2].size = master->size - 6 * master->erasesize - 
     148        trx_parts[2].size = master->size - uboot_len - nvram_len - art_len - 
    142149                trx_parts[1].size; 
    143150        trx_parts[2].mask_flags = 0; 
    144151 
    145152        trx_parts[3].name = "nvram"; 
    146         trx_parts[3].offset = master->size - 2 * master->erasesize; 
    147         trx_parts[3].size = master->erasesize; 
     153        trx_parts[3].offset = master->size - nvram_len - art_len; 
     154        trx_parts[3].size = nvram_len; 
    148155        trx_parts[3].mask_flags = MTD_WRITEABLE; 
    149156 
    150157        trx_parts[4].name = "art"; 
    151         trx_parts[4].offset = master->size - master->erasesize; 
    152         trx_parts[4].size = master->erasesize; 
     158        trx_parts[4].offset = master->size - art_len; 
     159        trx_parts[4].size = art_len; 
    153160        trx_parts[4].mask_flags = MTD_WRITEABLE; 
    154161 
    155162        trx_parts[5].name = "firmware"; 
    156         trx_parts[5].offset = 4 * master->erasesize; 
    157         trx_parts[5].size = master->size - 6 * master->erasesize; 
     163        trx_parts[5].offset = uboot_len; 
     164        trx_parts[5].size = master->size - uboot_len - nvram_len - art_len; 
    158165        trx_parts[5].mask_flags = 0; 
    159166 
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